Altera MAX 10 Embedded Memory - Manual (Page 25)

Signal Required Description
inclock
Optional The following list describes which of your memory
clock must be connected to the inclock port, and port
synchronization in different clock modes:
• Single clock—Connect your single source clock to
inclock
port and
outclock
port. All registered
ports are synchronized by the same source clock.
• Read/Write—Connect your write clock to
inclock
port. All registered ports related to write operation,
such as
data
port,
wraddress
port,
wren
port, and
byteena
port are synchronized by the write clock.
• Input/Output—Connect your input clock to
inclock
port. All registered input ports are
synchronized by the input clock.
inclocken
Optional Clock enable input for
inclock
port.
outclock
Optional The following list describes which of your memory
clock must be connected to the
outclock
port, and port
synchronization in different clock modes:
• Single clock—Connect your single source clock to
inclock
port and
outclock
port. All registered
ports are synchronized by the same source clock.
• Read/Write—Connect your read clock to
outclock
port. All registered ports related to read operation,
such as
rdaddress
port,
rdren
port, and
q
port are
synchronized by the read clock.
• Input/Output—Connect your output clock to
outclock
port. The registered
q
port is synchron‐
ized by the output clock.
outclocken
Optional Clock enable input for
outclock
port.
Table 4-2: RAM:1-Port IP Core Output Ports
Signal Required Description
q
Yes Data output from the memory. The
q
port must be
equal to the width data port.
RAM: 1-Port IP Core Parameters For MAX 10 Devices
Table 4-3: RAM: 1-Port IP Core Parameters for MAX 10 Devices
This table lists the IP core parameters applicable to MAX 10 devices.
Parameter Values Description
Parameter Settings: Widths/Blk Type/Clks
UG-M10MEMORY
2015.05.04
RAM: 1-Port IP Core Parameters For MAX 10 Devices 4-3
RAM: 1-Port IP Core References Altera Corporation
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