Altera MAX 10 Embedded Memory User Manual
Page 53
Figure 7-2: ROM: 2-PORT IP Core Signals with the Dual Clock: Use Separate 'Input' and 'Output' Clocks
Option Enabled
address_b[]
addressstall_a
inclock
inclocken
outclock
outclocken
q_a[]
out_aclr
address_a[]
addressstall_b
rden_a
rden_b
q_b[]
Figure 7-3: ROM: 2-PORT IP Core Signals with the Dual Clock: Use Separate Clocks for A and B Ports
Option Enabled
address_b[]
addressstall_a
clock_a
enable_a
clock_b
enable_b
q_a[]
aclr_a
address_a[]
addressstall_b
rden_a
rden_b
aclr_b
q_b[]
7-2
ROM: 2-PORT IP Core References
UG-M10MEMORY
2015.05.04
Altera Corporation
ROM: 2-PORT IP Core References
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