Altera MAX 10 Embedded Memory - Manual (Page 55)

Signal Required Description
inclock
Yes The following list describes which of your memory clock must be
connected to the
inclock
port, and port synchronization in
different clock modes:
• Single clock—Connect your single source clock to
inclock
port
and
outclock
port. All registered ports are synchronized by the
same source clock.
• Read/Write—Connect your write clock to
inclock
port. The
write clock synchronizes all registered ports related to write
operation, such as
data
port,
wraddress
port,
wren
port, and
byteena
port.
• Input/Output—Connect your input clock to
inclock
port. The
input clock synchronizes all registered input ports.
outclock
Yes The following list describes which of your memory clock must be
connected to the
outclock
port, and port synchronization in
different clock modes:
• Single clock—Connect your single source clock to inclock port
and
outclock
port. All registered ports are synchronized by the
same source clock.
• Read/Write—Connect your read clock to
outclock
port. The
read clock synchronizes all registered ports related to read
operation, such as
rdaddress
port,
rdren
port, and
q
port.
• Input/Output—Connect your output clock to
outclock
port.
The output clock synchronizes the registered
q
port.
inclocken
Optional Clock enable input for
inclock
port.
outclocken
Optional Clock enable input for
outclock
port.
aclr
Optional Asynchronously clear the registered input and output ports. The
asynchronous clear effect on the registered ports can be controlled
through their corresponding asynchronous clear parameter, such
as
indata_aclr
and
wraddress_aclr
.
Table 7-2: ROM: 2-PORT IP Core Output Signals
Signal Required Description
q_a
Yes Data output from port A of the memory. The
q_a
port is required
if you set the
operation_mode
parameter to any of the following
values:
•
SINGLE_PORT
•
BIDIR_DUAL_PORT
•
ROM
The width of the
q_a
port must be equal to the width of the
data_a
port.
7-4 ROM: 2-PORT IP Core Signals for MAX 10 Devices
UG-M10MEMORY
2015.05.04
Altera Corporation ROM: 2-PORT IP Core References
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