Altera MAX 10 Embedded Memory - Manual (Page 24)

RAM: 1-Port IP Core Signals For MAX 10 Devices
Table 4-1: RAM:1-Port IP Core Input Signals
Signal Required Description
data
Yes Data input to the memory. The
data
port is required
and the width must be equal to the width of the
q
port.
address
Yes Address input to the memory.
wren
Yes Write enable input for the
wraddress
port.
addressstall_a
Optional Address clock enable input to hold the previous address
of
address_a
port for as long as the
addressstall_a
port is high.
clock
Yes The following list describes which of your memory
clock must be connected to the clock port, and port
synchronization in different clocking modes:
• Single clock—Connect your single source clock to
clock
port. All registered ports are synchronized by
the same source clock.
• Read/Write—Connect your write clock to
clock
port. All registered ports related to write operation,
such as
data_a
port,
address_a
port,
wren_a
port,
and
byteena_a
port are synchronized by the write
clock.
• Input/Output—Connect your input clock to
clock
port. All registered input ports are synchronized by
the input clock.
• Independent clock—Connect your port A clock to
clock
port. All registered input and output ports of
port A are synchronized by the port A clock.
clkena
Optional Clock enable input for
clock
port.
rden
Optional Read enable input for
rdaddress
port.
aclr
Optional Asynchronously clear the registered input and output
ports. The asynchronous clear effect on the registered
ports can be controlled through their corresponding
asynchronous clear parameter, such as indata_aclr,
wraddress_aclr, and so on.
4-2 RAM: 1-Port IP Core Signals For MAX 10 Devices
UG-M10MEMORY
2015.05.04
Altera Corporation RAM: 1-Port IP Core References
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