Altera MAX 10 Embedded Memory - Manual (Page 49)

Signal Required Description
outclocken
Optional Clock enable input for
outclock
port.
Table 6-2: ROM: 1-PORT IP Core Output Signals
Signal Required Description
q
Yes Data output from the memory. The
q
port is required,
and must be equal to the width data port.
ROM: 1-PORT IP Core Parameters for MAX 10 Devices
Table 6-3: ROM: 1-Port IP Core Parameters for MAX 10 Devices
This table lists the IP core parameters applicable to MAX 10 devices.
Option Legal Values Description
Parameter Settings: General
How wide should the 'q' output bus be?
1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11,
12, 13, 14, 15, 16, 17, 18, 19,
20, 21, 22, 23, 24, 25, 26, 27,
28, 29, 30, 31, 32, 36, 40, 48,
64, 72, 108, 128, 144, and 256.
Specifies the width of the 'q'
output bus in bits.
How many -bit words of memory? 32, 64, 128, 256, 512, 1024,
2048, 4096, 8192, 16384,
32768, and 65536.
Specifies the number of
-bit words.
What should the memory block type be?
• Auto
• M9K
Specifies the memory block
type. The types of memory
block that are available for
selection depends on your
target device.
Set the maximum block depth to
• Auto
• 32
• 64
• 128
• 256
• 512
• 1024
• 2048
• 4096
• 8192
Specifies the maximum
block depth in words.
6-4 ROM: 1-PORT IP Core Parameters for MAX 10 Devices
UG-M10MEMORY
2015.05.04
Altera Corporation ROM: 1-PORT IP Core References
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