Altera MAX 10 Embedded Memory - Manual (Page 50)

Option Legal Values Description
What clocking method would you like to
use?
• Single clock
• Dual clock: use separate
‘input’ and ‘output’ clocks
Specifies the clocking
method to use.
• Single clock—A single
clock and a clock enable
controls all registers of
the memory block.
• Dual clock: use separate
‘input’ and ‘output’
clocks—An input and an
output clock controls all
registers related to the
data input and output to/
from the memory block
including data, address,
byte enables, read
enables, and write
enables.
Parameter Settings: Regs/Clkens/Aclrs
Which ports
should be
registered?
• 'address' input port
• 'q' output port
On/Off Specifies whether to register
the read or write input and
output ports.
Create one clock enable signal for each
clock signal.
On/Off Specifies whether to turn on
the option to create one
clock enable signal for each
clock signal.
More Options • Clock enable options
• Use clock enable
for port A input
registers
• Use clock enable
for port A output
registers
• Address options
• Create an 'address‐
stall_a' input port
On/Off
• Clock enable options—
Clock enable for port B
input and output
registers are turned on by
default. You only need to
specify whether to use
clock enable for port A
input and output
registers.
• Address options—
Specifies whether to
create clock enables for
address registers. You
can create these ports to
act as an extra active low
clock enable input for the
address registers.
Create an ‘aclr’ asynchronous clear for the
registered ports.
On/Off Specifies whether to create
an asynchronous clear port
for the registered ports.
UG-M10MEMORY
2015.05.04
ROM: 1-PORT IP Core Parameters for MAX 10 Devices 6-5
ROM: 1-PORT IP Core References Altera Corporation
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