Altera MAX 10 Embedded Memory User Manual
Page 30
Figure 5-2: RAM: 2-Port IP Core Signals with the One Read Port and One Write Port, and Dual Clock: Use
Separate 'Read' and 'Write' Clocks Options Enabled
data[]
wren
rdaddress[]
wr_addressstall
wrclock
wrclocken
rdclock
rdinclocken
q[]
rd_aclr
wraddress[]
rden
rd_addressstall
rdoutclocken
byteena_a[]
rdclocken
Figure 5-3: RAM: 2-Port IP Core Signals with the One Read Port and One Write Port, and Dual Clock: Use
Separate 'Input' and 'Output' Clocks Options Enabled
data[]
wren
rdaddress[]
rden
wr_addressstall
inclock
inclocken
outclock
outclocken
q[]
in_aclr
out_aclr
wraddress[]
byteena_a[]
rd_addressstall
5-2
RAM: 2-PORT IP Core References
UG-M10MEMORY
2015.05.04
Altera Corporation
RAM: 2-PORT IP Core References
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