Altera MAX 10 Embedded Memory User Manual
Page 45
Option
Legal Values
Description
Do you want to specify the initial content
of the memory?
• No, leave it blank
• Yes, use this file for the
memory content data
Specifies the initial content
of the memory.
• To initialize the memory
to zero, select No, leave it
blank.
• To use a Memory Initiali‐
zation File (.mif) or a
Hexadecimal (Intel-
format) File (.hex), select
Yes, use this file for the
memory content data.
Note: The configuration
scheme of your
device is Internal
Configuration. In
order to use
memory initiali‐
zation, you must
select a single
image configura‐
tion mode with
memory initiali‐
zation, for
example the
Single
Compressed
Image with
Memory Initiali‐
zation option.
You can set the
configuration
mode on the
Configuration
page of the
Device and Pin
Options dialog
box.
The initial content file should conform to
which port's dimension?
• PORT_A
• PORT_B
Specifies which port's
dimension that the initial
content file should conform
to.
UG-M10MEMORY
2015.05.04
RAM: 2-Port IP Core Parameters for MAX 10 Devices
5-17
RAM: 2-PORT IP Core References
Altera Corporation
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)