Shift register (ram-based) ip core references, Shift register (ram-based) ip core references -1 – Altera MAX 10 Embedded Memory User Manual
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Shift Register (RAM-based) IP Core References
8
2015.05.04
UG-M10MEMORY
The Shift Register (RAM-based) IP core contains additional features not found in a conventional shift
register. You can use the memory blocks as a shift-register block to save logic cells and routing resources.
You can cascade memory blocks to implement larger shift registers.
Figure 8-1: Shift Register (RAM-based) IP Core Signals
shift_in[]
clock
clken
aclr
shiftout[]
taps[]
Shift Register (RAM-based) IP Core Signals for MAX 10 Devices
Table 8-1: Shift Register (RAM-based) IP Core Input Signals
Signal
Required
Description
shiftin[]
Yes
Data input to the shifter. Input port
WIDTH
bits wide.
clock
Yes
Positive-edge triggered clock.
clken
No
Clock enable for the
clock
port.
clken
defaults to VCC.
aclr
No
Asynchronously clears the contents of the shift register chain. The
shiftout outputs are cleared immediately upon the assertion of the
aclr
signal.
Table 8-2: Shift Register (RAM-based) IP Core Output Signals
Signal
Required
Description
shiftout[]
Yes
Output from the end of the shift register. Output port
WIDTH
bits wide.
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