INFICON Composer Gas Concentration Controller - Manual (Page 59)

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Composer Operating Manual
2.6.2.5 Sensor Temperature Control
U3, U5D, U13, U14, VR1,
U19, Q2
Temperature of the sensor is measured by a Crystal Semiconductor A/D
converter CS5516-AS (U13). The 16 bit converter is configured to measure a
range of temperature from 0 to 80 °C thus yielding a resolution of 1.22e-3
degrees. Precision is maintained by the use of .1% resisters with low TCO
(R25,26,27,32,33) and AC excitation to eliminate thermocouple effects. The AC
excitation is produced by the combination of a 78L05CZ(U3), LF347(U5D), and
a 7002SMT CMOS transistor and is driven by BX1 of the CS5516-AS. 10 Volts
P-P excitation is produced by the LF347 acting as a unity gain inverter when Q1
conducts and as a unity gain buffer when Q1 is off. The 5 volts supplied by the
78L05CZ does not need to be precise because the A/D conversion is done
ratiometrically. Data and configuration parameter values are serially
communicated through the FPGA and accessible in a parallel form by either the
CPU or DSP.
The heater section uses an 8-bit PWM output of the CPU to switch the raw 24
volts and apply it to the sensor heating elements. A HCPL-0201(U19) is used
to isolate the PWM signal from the 24 volt supply along with a 78L15(VR1)
regulator for the logic side of the HCPL-0201. C88 and D9 prevents the heater
from being full on should the PWM stop and be inadvertently left in a high state.
A RFD3055SM(Q2) is used as the power switching transistor and the
combination of L8, C125, and D16 filters the output to the sensor.
2.6.2.6 I/O
U18, U20, U6, U17
Analog I/O uses two 16-bit AD699(U18,U20) precision D/A converters for +/- 10
volt outputs (CONCENTRATION OUT, CONTROL OUT). Pots R18,R19,R53
and R57 are provided for gain and offset trim. Data to the D/A’s is via a 16-bit
CPU data bus. A CS5501(U17) is used for the analog input (CONTROL IN). The
CS5501 is internally calibrated for zero on power up and gain is set by a
LT1019(U6) reference trimmed by R17. Data is sent by a serial bus to the FPGA
where it’s converted to a parallel format and made available to either the CPU
or DSP.
U1, U2, U12, U16
Five relay outputs are controlled by a 74HC595(U1) serial to parallel shift
register and a ULN2003D(U2) driver. Also 7 digital inputs are provided by a
ULN2003D(16) driver to a 74HC165(U12) parallel to serial shift register. The
serial communications are made directly by CPU I/O pins.