INFICON Composer Gas Concentration Controller - Manual (Page 58)

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Composer Operating Manual
2.6.2.3 FPGA
U33
The FPGA is an Actel A1010B programmed to act as an interface to the various
sections of the system. It provides a bi-directional parallel port between the
CPU and the DSP along with the necessary logic for handshaking and power
up boot loading of the DSP by the CPU. The FPGA also performs a serial to
parallel, parallel to serial conversion and handshaking to read and write the
temperature A/D by either the CPU or the DSP. It also provides a second serial
to parallel interface and handshaking for the A/D converter that monitors the
CONTROL IN signal from the back panel that is also accessible by either the
CPU or the DSP. Clocks for the rest of the system are also provided by the
FPGA by dividing down the DSP clock producing 9.8304, 4.9152, and 2.4576
MHz outputs. Resets for the DSP and sensor electronics are also provided by
FPGA logic allowing the CPU to individually set, clear and monitor their state.
2.6.2.4 Cell Excitation
U5, U24, U29, U8, U9
One half of a LF347(U5A,C) quad op-amp is utilized to amplify the signal from
the sensor and to also convert it from single ended to differential before
presenting it to a TLC320AC02(U24) CODEC (Coder/Decoder). Also U5B of
the LF347 supplies the 1.25 volt microphone bias to the sensor by dividing
VMID of the TLC320AC02 by two. The TLC320AC02(U24) is a 14 bit CODEC
that simultaneously performs an A/D and D/A function sending and receiving
data between it and the DSP via a serial link. The TLC320AC02 has eight
internal registers for the purposes of controlling filters, sample rate, and
attenuators for both input and output signals. A second TLC320AC02(U29)
operating as a slave to U24 is used to generate a second drive signal to cancel
mechanically coupled signals from the first drive signal. Two MC34119D’s
(U9,U8) are used as power amplifiers for the drive and anti-drive signals to the
sensor speakers.