11 asp tdm tx control 1–4, 12 asp tdm tx enable 1–6, 13 asp control 2 – Cirrus Logic CS53L30 User Manual
Page 50: 14 soft ramp control, P_sd, Digsft, P. 50, Asp tdm tx control 1–4, Address 0x0e–0x11, Asp tdm tx enable 1–6
50
DS992F1
CS53L30
7.11 ASP TDM TX Control 1–4
7.11 ASP TDM TX Control 1–4
Address 0x0E–0x11
R/W
7
6
5
4
3
2
1
0
ASP_CHx_TX_STATE
—
ASP_CHx_TX_LOC[5:0]
Default
0
0
1
0
1
1
1
1
Bits
Name
Description
7
ASP_
CHx_TX_
STATE
ASP TDM TX state control. Configures the state of the data for the ASP on Channel x.
0 (Default) Channel data is available
1 Channel data is not available
6
—
Reserved
5:0
ASP_
CHx_TX_
LOC
ASP TDM TX location control. Configures the first TDM slot in which the respective data set is to be transmitted on the ASP.
describes configuration and priorities. To avoid overlap, the following channel’s start slot must also be configured.
00 0000 Slot 0 …
10 1111 (Default) Slot 47
11 0000–11 1111 Reserved
7.12 ASP TDM TX Enable 1–6
Address 0x12–0x17
R/W
7
6
5
4
3
2
1
0
0x12
ASP_TX_ENABLE[47:40]
0x13
ASP_TX_ENABLE[39:32]
0x14
ASP_TX_ENABLE[31:24]
0x15
ASP_TX_ENABLE[23:16]
0x16
ASP_TX_ENABLE[15:8]
0x17
ASP_TX_ENABLE[7:0]
Default
0
0
0
0
0
0
0
0
Bits
Name
Description
7:0 ASP_TX_
ENABLEx
ASP TDM TX Enable. Each bit individually enables or disables one of 48 slots for transmission on ASP_SDOUT1 pin. TDM
slots 7–0 are enabled by ASP_TX_ENABLE[7:0], slots 15–8 are enabled by ASP_TX_ENABLE[15:8], and so on.
0 (Default) Not enabled (Hi-Z)
1 Enabled (driven)
7.13 ASP Control 2
Address 0x18
R/W
7
6
5
4
3
2
1
0
—
ASP_SDOUT2_PDN
—
ASP_SDOUT2_DRIVE
Default
0
0
0
0
0
0
0
0
Bits
Name
Description
7
—
Reserved
6
ASP_
SDOUT2_
PDN
ASP_SDOUT2 output path power down. Configures the ASP_SDOUT2 path’s power state for I
2
S Mode (ASP_TDM_PDN = 1).
0 (Default) Powered up
1 Powered down, ASP_SDOUT2 is Hi-Z. Setting this bit does not tristate the serial port clock. If ASP_TDM_PDN is cleared,
setting this bit does not affect ASP_SDOUT2.
5:1
—
Reserved
0
ASP_
SDOUT2_
DRIVE
ASP_SDOUT2 output drive strength.
describes drive-strength specifications.
0 (Default) Normal
1 Decreased
7.14 Soft Ramp Control
Address 0x1A
R/W
7
6
5
4
3
2
1
0
—
DIGSFT
—
Default
0
0
0
0
0
0
0
0
Bits
Name
Description
7:6
—
Reserved
5
DIGSFT
Digital soft ramp. Configures an incremental volume ramp of all digital volumes from the current level to the new level. The
soft ramp rate is fixed at 8 FS
int
periods per step. Step size is fixed at 0.125 dB.
0 (Default) Do not occur with a soft ramp
1 Occurs with a soft ramp
4:0
—
Reserved