Cirrus Logic CS53L30 - Manual (Page 33)

DS992F1 33
CS53L30
4.8 Synchronous Sample-Rate Converter (SRC)
To maximize bus usage, the device supports hand-off between devices in a half clock cycle, which means no clock cycles
have to be sacrificed during the hand-off between two devices. This behavior is shown in
Table 3-12 . If SHIFT_LEFT (see
p. 45 ) is set, the hand-off between two devices has no margin and brief bus contention may occur.
As shown in Table 3-12 , the transmission of the last LSB before a disabled slot transitions to Hi-Z earlier than a normal
transition to allow more time for the data being driven by the succeeding device to become stable on the bus before being
clocked in by the receiver. This minimizes the risk of bus contention and ensures that any data loss affects only the LSB
of a given data set, not the MSB. Bus sharing after the 48-slot window is not supported and SDOUT will be driven for up
to 16 SCLKs following the 48th slot. After the 16th SCLK, SDOUT is driven low for the remainder of the frame. The
expected behavior follows:
• As long as SCLK is toggling, data transfers of up to 3 bytes can be initiated from any of the 48 slots, including the
last two (Slots 46–47).
If a transfer is configured from either of the last two slots (Slot 46 or 47), SDOUT drives all 24 bits of specified data,
after which SDOUT is driven low.
• If Slot 47 is not enabled, SDOUT is set to Hi-Z and remains at Hi-Z until the end of the frame.
4.8 Synchronous Sample-Rate Converter (SRC)
The CS53L30 includes dual decimation-mode synchronous stereo SRC to bridge potentially different sample rates in the
system. Multirate digital signal-processing techniques are used to conceptually up-sample the incoming data to a very high
rate and then down-sample to the outgoing rate. Internal filtering is designed so that a full input audio bandwidth of 20 kHz
is preserved if the output sample rate is greater than or equal to 44.1 kHz. Any jitter in the incoming signal has little effect
on the dynamic performance of the rate converter and has no influence on the output clock.
The MCLK to LRCK ratios defined in Table 4-2 must be followed to achieve the sample rates in either Master or Slave
Mode. The coefficients of a linear time varying filter are predetermined to produce the output sample rates in Table 4-2 if
the MCLK to LRCK ratios are used.
The gain from INx to SDOUT through the SRC is dependent on output sample rate (i.e., LRCK frequency) and MCLK
frequency.
Table 4-4 shows the gain with a 1-kHz full scale input over the supported sample rates and MCLK frequencies.
Table 4-4. Synchronous SRC Gain Versus Sample Rate
MCLK
ext
(kHz) LRCK (kHz) Gain (dB) 1
1.Gain with a 1-kHz, full scale input sine wave, 0-dB gain preamp setting, and 0-dB PGA gain
setting, ADCx_NOTCH_DIS = 1, ADCx_HPF_EN = 0.
5.6448, 11.2896 11.025 –0.173
22.050 –0.170
44.100 –0.168
6.0000, 6.1440, 12.0000, 12.2880 8.000 –0.313
11.025 –0.291
12.000 –0.172
16.000 –0.307
22.050 –0.288
24.000 –0.169
32.000 –0.305
44.100 –0.287
48.000 –0.167
19.2000 8.000 –0.383
11.025 –0.241
12.000 –0.231
16.000 –0.376
22.050 –0.236
24.000 –0.231
32.000 –0.374
44.100 –0.238
48.000 –0.231