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5 serial-port sample rates, Table 4-2, Section 4.6.5 – Cirrus Logic CS53L30 User Manual

Page 27: Mclk de, Lists supp, Cs53l30

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DS992F1

27

CS53L30

4.6 Serial Ports

4.6.5

Serial-Port Sample Rates

Table 4-2

lists the supported sample rates. Before making changes to any clock setting or frequency, the device must be

powered down by setting either the PDN_ULP or PDN_LP bit.

v

Table 4-2. Supported Master Clocks and Sample Rates

MCLK

EXT

(MHz)

MCLK

INT

(MHz)

INTERNAL_FS_RATIO

Setting (MCLK

INT

/FS

INT

)

MCLK_INT_SCALE

MCLK

INT

Scaling

ASP_RATE

Fs

INT

(kHz)

LRCK (Fs

EXT

)

(kHz)

MCLK

EXT

/

LRCK Ratio

1

6.0000 6.0000

(MCLK_

DIV = 00)

0

0 (disabled)

0001

48.000

8.000

750

1 (

4)

0001

12.000

8.000 750

0 (disabled)

0010

48.000

11.025

80000/147

1 (

4)

0010

12.000

11.025 80000/147

X

0011

48.000

11.029

2

544

0 (disabled)

0100

48.000

12.000

500

1 (

4)

0100

12.000

12.000 500

0 (disabled)

0101

48.000

16.000

375

1 (

2)

0101

24.000

16.000 375

0 (disabled)

0110

48.000

22.050

40000/147

1 (

2)

0110

24.000

22.050 40000/147

X

0111

48.000

22.059

2

272

0 (disabled)

1000

48.000

24.000

250

1 (

2)

1000

24.000

24.000 250

X

1001

48.000

32.000

187.5

X

1010

48.000

44.100

20000/147

X

1011

48.000

44.118

2

136

X

1100

48.000

48.000

125

12.0000 6.0000

(MCLK_

DIV = 01)

0

0 (disabled)

0001

48.000

8.000

1500

1 (

4)

0001

12.000

8.000 1500

0 (disabled)

0010

48.000

11.025

160000/147

1 (

4)

0010

12.000

11.025 160000/147

X

0011

48.000

11.029

2

1088

0 (disabled)

0100

48.000

12.000

1000

1 (

4)

0100

12.000

12.000 1000

0 (disabled)

0101

48.000

16.000

750

1 (

2)

0101

24.000

16.000 750

0 (disabled)

0110

48.000

22.050

80000/147

1 (

2)

0110

24.000

22.050 80000/147

X

0111

48.000

22.059

2

544

0 (disabled)

1000

48.000

24.000

500

1 (

2)

1000

24.000

24.000 500

X

1001

48.000

32.000

375

X

1010

48.000

44.100

40000/147

X

1011

48.000

44.118

2

272

X

1100

48.000

48.000

250

5.6448 5.6448

(MCLK_

DIV = 00)

1

0 (disabled)

0100

44.100

11.025

512

1 (

4)

0100

11.025 11.025

512

0 (disabled)

1000

44.100

22.050

256

1 (

2)

1000

22.050 22.050

256

X

1100

44.100

44.100

128

11.2896 5.6448

(MCLK_

DIV = 01)

1

0 (disabled)

0100

44.100

11.025

1024

1 (

4)

0100

11.025 11.025

1024

0 (disabled)

1000

44.100

22.050

512

1 (

2)

1000

22.050 22.050

512

X

1100

44.100

44.100

256