Cirrus Logic CS53L30 - Manual (Page 35)

DS992F1 35
CS53L30
4.12 MUTE Pin
To use thermal overload notification, do the following:
1. Enable the thermal-sense circuitry by programming THMS_PDN (see p. 48 ).
2. Set M_THMS_TRIP (see p. 57 ) if an interrupt is desired when THMS_TRIP toggles from 0 to 1.
3. Monitor (read after interrupt [QFN only] or poll) the thermal overload interrupt status bit and respond accordingly.
Except for the associated status bit, the operation of the CS53L30 is not affected by the thermal overload notification.
4.12 MUTE Pin
If MUTE is asserted, all four audio channels are muted. In addition, other circuits can be powered down; for example,
power down all ADCs and MIC_BIAS outputs or individual ADC channels or MIC_BIAS outputs by programming the MUTE
pin control registers (
Section 7.17 and Section 7.18 list programming options).
If DIGSFT (see p. 50 ) is set when the MUTE pin is asserted or deasserted, the corresponding volume ramp occurs before
the power-state change.
4.13 Power-Up and Power-Down Control
The CS53L30 offers the following for managing power:
• The RESET pin
• The PDN_ULP bit (see p. 47 )
• The PDN_LP bit (see p. 47 )
• Individual x_PDN bits
In addition, the MUTE pin can also be programmed to affect any or all of the PDNs. When RESET is asserted, all blocks
are powered down and reset to their default values. (See
Table 3-14 for minimum RESET pulse width.) In power down
(PDN_ULP = 1 or PDN_LP = 1), all blocks except the I 2 C control port are powered down. PDN_ULP is used for
ultralow-power operation as it powers down the internal bandgap, VREF, VCM, weak VCM, as well as the ADCs, state
machines, etc. PDN_LP is used for low-power operation and only powers down the ADCs, state machines, etc. PDN_ULP
and PDN_LP can be used to control the sequence of what is powered in the CS53L30. When both PDN_ULP and PDN_
LP are cleared, all blocks are powered up depending on the individual x_PDN bits. If both PDN_ULP and PDN_LP are
cleared simultaneously, the bandgap, VREF, and VCM circuits are not available for approximately 20 ms. To effect a more
deterministic power-up of the ADCs, internal dividers, state machines, etc., the following sequence is recommended:
1. Set both PDN_ULP and PDN_LP.
2. Release PDN_ULP.
3. Wait 50 ms before releasing PDN_LP.
4.14 I 2 C Control Port
The control port is used to access the registers allowing the device to be configured for the desired operational modes and
formats. The operation of the control port may be completely asynchronous with respect to the audio sample rates.
However, to avoid potential interference problems, the control port pins should remain static if no operation is required.
SDA is a bidirectional data line. Data is clocked into and out of the CS53L30 by the clock, SCL. The signal timings for read
and write cycles are shown in
Fig. 4-18 – Fig. 4-20 . A Start condition is defined as a falling transition of SDA while the clock
is high. A Stop condition is defined as a rising transition of SDA while the clock is high. All other transitions of SDA occur
while the clock is low.
The first byte sent to the CS53L30 after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a
read, low for a write) in the LSB. To communicate with the CS53L30, the chip address field is dependent upon the state
of AD0 and AD1 after RESET has been deasserted and should match 1001 000 if AD1,0 = 00, 1001 001 if AD1,0 = 01,
1001 010 if AD1,0 = 10, and 1001 011 if AD1,0 = 11.