2 interrupt handling with the qfn package, 4 capture-path inputs, Section 4.4 – Cirrus Logic CS53L30 User Manual

Page 20: Fig. 4-2, Cs53l30

DS992F1

CS53L30

4.4 Capture-Path Inputs

4.3.2

Interrupt Handling with the QFN Package

The interrupt pin (INT) is implemented on the QFN package. Interrupt status bits can be individually masked by setting
corresponding bits in the interrupt mask register (see

Section 7.35

). The configuration of mask bits determines which

events cause the assertion of INT:

•

When an unmasked interrupt status event is detected, the status bit is set and INT is asserted.

•

When a masked interrupt status event is detected, the interrupt status bit is set, but INT is not affected.

Once INT is asserted, it remains asserted until all status bits that are unmasked and set have been read. If a condition
remains present and the status bit is read, although INT is deasserted, the status bit remains set.

To clear any status bits set due to the initiation of a path or block, all interrupt status bits should be read after reset and
before normal operation begins. Otherwise, unmasking any previously set status bits causes INT to assert.

Figure 4-2. Example of Rising-Edge Sensitive, Sticky, Interrupt Status Bit Behavior (INT Pin in QFN only)

4.4 Capture-Path

Inputs

This section describes the line in and mic inputs.

Fig. 4-3

shows the capture-path signal flow.

Figure 4-3. Capture-Path Signal Flow

Raw signal feeding
status register bit

Status register bit

___
INT pin

Status read value

Read Source