6 i2s format, Section 4.6.6, Cs53l30 – Cirrus Logic CS53L30 User Manual
Page 28: S format
28
DS992F1
CS53L30
4.6 Serial Ports
4.6.6
I
2
S Format
I
2
S format offers the following:
•
Up to 24 bits/sample of stereo data can be transferred (see
•
Master or slave timing may be selected.
•
LRCK (i.e., ASP_LRCK/FSYNC) identifies the start of a new sample word and the active stereo channel (A or B).
•
Data is clocked out of the ASP_SDOUTx output using the falling edge of SCLK (i.e., ASP_SCLK).
•
Bit order is MSB to LSB.
shows the signaling for I
2
S format.
6.1440 6.1440
(MCLK_
DIV = 00)
1
0 (disabled)
0001
48.000
8.000
768
1 (
4)
0001
12.000 8.000
768
0 (disabled)
0010
48.000
11.025
81920/147
1 (
4)
0010
12.000 11.025 81920/147
0 (disabled)
0100
48.000
12.000
512
1 (
4)
0100
12.000
12.000 512
0 (disabled)
0101
48.000
16.000
384
1 (
2)
0101
24.000 16.000
384
0 (disabled)
0110
48.000
22.050
40960/147
1 (
2)
0110
24.000 22.050 40960/147
0 (disabled)
1000
48.000
24.000
256
1 (
2)
1000
24.000 24.000
256
X
1001
48.000
32.000
192
X
1010
48.000
44.100
20480/147
X
1100
48.000
48.000
128
12.2880 6.1440
(MCLK_
DIV = 01)
1
0 (disabled)
0001
48.000
8.000
1536
1 (
4)
0001
12.000 8.000
1536
0 (disabled)
0010
48.000
11.025
163840/147
1 (
4)
0010
12.000 11.025 163840/147
0 (disabled)
0100
48.000
12.000
1024
1 (
4)
0100
12.000 12.000
1024
0 (disabled)
0101
48.000
16.000
768
1 (
2)
0101
24.000 16.000
768
0 (disabled)
0110
48.000
22.050
81920/147
1 (
2)
0110
24.000 22.050 81920/147
0 (disabled)
1000
48.000
24.000
512
1 (
2)
1000
24.000 24.000
512
X
1001
48.000
32.000
384
X
1010
48.000
44.100
40960/147
X
1100
48.000
48.000
256
19.2000 6.4000
(MCLK_
DIV = 10)
1
0 (disabled)
0001
50.000
8.000
2400
1 (
4)
0001
12.500 8.000
2400
0 (disabled)
0010
50.000
11.025
256000/147
1 (
4)
0010
12.500 11.025 256000/147
0 (disabled)
0100
50.000
12.000
1600
1 (
4)
0100
12.500 12.000
1600
0 (disabled)
0101
50.000
16.000
1200
1 (
2)
0101
25.000 16.000
1200
0 (disabled)
0110
50.000
22.050
128000/147
1 (
2)
0110
25.000 22.050 128000/147
0 (disabled)
1000
50.000
24.000
800
1 (
2)
1000
25.000 24.000
800
X
1001
50.000
32.000
600
X
1010
50.000
44.100
64000/147
X
1100
50.000
48.000
400
1.The internal synchronous SRC guarantees the MCLK
EXT
/LRCK ratio when the CS53L30 is a PCM bus master. If the CS53L30 is a PCM slave, the
PCM master must provide the exact MCLK/LRCK ratio.
2.Supported only if CS53L30 is a PCM bus slave.
Table 4-2. Supported Master Clocks and Sample Rates (Cont.)
MCLK
EXT
(MHz)
MCLK
INT
(MHz)
INTERNAL_FS_RATIO
Setting (MCLK
INT
/FS
INT
)
MCLK_INT_SCALE
MCLK
INT
Scaling
ASP_RATE
Fs
INT
(kHz)
LRCK (Fs
EXT
)
(kHz)
MCLK
EXT
/
LRCK Ratio
1