Cirrus Logic CS53L30 - Manual (Page 19)

DS992F1 19
CS53L30
4.2 Resets
The CS53L30 consists of the following blocks:
• Interrupts. The CS53L30 QFN package includes an open-drain, active-low interrupt output, INT. Section 4.3
describes interrupts.
• Capture-path inputs. The analog input block, described in Section 4.4 , allows selection from either analog line-level,
or analog mic sources. The selected analog source is fed into a mic preamplifier (when applicable) and then into a
PGA, before entering the ADC. The pseudodifferential input configuration can provide noise rejection for
single-ended analog inputs. The digital mic inputs (IN1+/DMIC1_SD, IN3+/DMIC2_SD) connect directly to the
decimators.
• Serial ports. The CS53L30 has either two I 2 S output ports or one TDM output port allowing communication to other
devices in the system such as applications processors. The serial data ports are described in Section 4.6.1 . The
TDM port allows multidrop operation (i.e., tristate capable SDOUT driver) for sharing the TDM bus between multiple
devices, and flexible data structuring via control port registers.
• Synchronous sample rate converter (SRC). The SRC, described in Section 4.8 , is used to bridge different sample
rates at the serial port within the digital-processing core.
• Multichip synchronization protocol. Some applications require more than four simultaneous audio channels
requiring multiple CS53L30s. In a subset of these multidevice applications, special attention to phase alignment of
audio channels is required. The CS53L30 has a synchronization protocol to align all audio channels and minimize
interchannel phase mismatch.
Section 4.9 describes the synchronization protocol.
• Thermal overload notification. The CS53L30 can be configured to notify the system processor that its die
temperature is too high. This functionality is described in
Section 4.11 .
• Mute pin. The CS53L30 audio outputs can be muted with the assertion of the register-programmable MUTE pin.
The MUTE pin function can also be programmed to power-down ADCs, MICx_BIAS, etc., by setting the appropriate
bits in
Section 7.17 and Section 7.18 . Section 4.12 describes the MUTE pin functionality.
• Power management. Several registers provide independent power-down control of the analog and digital sections
of the CS53L30, allowing operation in select applications with minimal power consumption. Power management
considerations are described in
Section 4.13 .
• Control port operation. The control port is used to access the registers allowing the CS53L30 to be configured for
the desired operational modes and formats. The operation of the control port may be completely asynchronous with
respect to the audio sample rates. To avoid interference problems, the control port pins must remain static if no
operation is required. Control port operation is described in
Section 4.14 .
4.2 Resets
The CS53L30 can be reset only by asserting RESET. When RESET is asserted, all registers and all state machines are
immediately set to their default values/states. No operation can begin until RESET is deasserted. Before normal operation
can begin, RESET must be asserted at least once after the VA supply is brought up. The VP supply should be brought up
before the VA supply.
4.3 Interrupts
The status of events that may require special attention is recorded in the interrupt status register (see Section 7.36 ).
Interrupt status bits are sticky and read-to-clear: That is, once set, they remain set until the status register is read and the
associated interrupt condition is no longer present.
4.3.1 Interrupt Handling with the WLCSP Package
If the WLCSP package is used, events and conditions are detected in software by polling the interrupt status register. The
mask register can be ignored (see
Section 7.35 ). Status register bits are cleared when read, as Fig. 4-2 shows. If the
underlying condition remains valid, the bit remains set even after the status register is read.