Cirrus Logic CS53L30 - Manual (Page 2)

2 DS992F1
CS53L30
General Description
The CS53L30 is a high-performance, low-power, quad-channel ADC. It is designed for use in multiple-mic applications
while consuming minimal board space and power.
The flexible ADC inputs can accommodate four channels of analog mic or line-input data in differential, pseudodifferential,
or single-ended mode, or four channels of digital mic data. The analog input path includes a +10- to +20-dB boost and a
–6- to +12-dB PGA. Digital mic data bypasses the analog gain circuits and is fed directly to the decimators.
Four mic bias generators are integrated into the device. The device also includes two digital mic serial clock outputs.
The CS53L30 includes several digital signal processing features such as high-pass filters, noise gate, and volume control.
The device can output its four channels of audio data over two I 2 S ports or a single TDM port. Additionally, up to four
CS53L30s can be used to output up to 16 channels of data over a single TDM line. This is done by setting the appropriate
frame slots for each device, and each device then alternates between outputting data and setting the output pin to high
impedance.
The CS53L30 can operate as a serial port clock master or slave. In Master Mode, clock dividers are used to generate the
internal master clock and audio clocks from either the 6-/12-MHz, 6.144-/12.288-MHz, 5.6448-/11.2896-MHz, or 19.2-MHz
master clock.
The device is powered from VA, a 1.8-V nominal supply and VP, a typical battery supply. An internal LDO on the VA supply
powers the device’s digital core. The VP supply powers the mic bias generators and the AFE.
The CS53L30 is controlled by an I 2 C control port. A reset pin is also included. The device is available in a 30-ball 0.4-mm
pitch WLCSP package and 32-pin 5 x 5-mm QFN package.