Cirrus Logic CS53L30 - Manual (Page 23)

DS992F1 23
CS53L30
4.5 Digital Microphone (DMIC) Interface
4.4.2 External Coupling Capacitors
The analog inputs are internally biased to the internally generated common-mode voltage (VCM). Input signals must be
AC coupled using external capacitors (C
INM
) with values consistent with the desired HPF design. The analog input
resistance may be combined with an external capacitor to achieve the desired cutoff frequency.
Eq. 4-1 provides an example for mic inputs.
Equation 4-1. External Coupling Capacitors—Mic Inputs
Eq. 4-2 provides an example for line inputs.
Equation 4-2. External Coupling Capacitors—Line Inputs
4.4.3 Capture-Path Pin Biasing
Capture-path pins are internally biased during normal operation. When connecting analog sources to the CS53L30, the
input must be AC-coupled with an external capacitor. These sources may bias the analog inputs:
• Quick-Ref. After an analog input is powered up, the Quick-Ref buffer charges the external capacitor with a
low-impedance bias source to minimize startup time.
• Weak VCM. When ADCx is powered up, the weak VCM biases unselected inputs to minimize coupling conditions.
• ADCx_PREAMP. When ADCx is powered up, ADCx_PREAMP biases the selected channel.
See Fig. 4-5 for the location of each bias source.
4.4.4 Soft Ramping (DIGSFT)
DIGSFT (see p. 50 ) controls whether digital volume updates are applied slowly by stepping through each volume control
setting with a delay between steps equal to an integer number of FS
int
periods. The amount of delay between steps is fixed
at 8 FS
int
periods. The step size is fixed at 0.125 dB.
When enabled, soft ramping is applied to all digital volume changes. Digital volume is affected by the following:
1. Writing directly to the ADC digital volume registers, ADC1x_VOL or ADC2x_VOL (see p. 54 and p. 56 )
2. Enabling or disabling mute by driving a signal to the MUTE pin
3. Muting that is applied automatically by the noise gate
4. Muting that is applied automatically during power up and power down
If digital boost is disabled and the ADC digital volume is set to any value from 0x0C to 0x7F (all equivalent to +12 dB), the
soft ramp first steps through the +12-dB settings in the same manner as the remainder of the volume settings. Soft ramp
timing calculations must include these additional steps. For example, if the ADC digital volume setting is changed from
0x10 (+12 dB) to 0x00 (0 dB), the first 32 soft ramp steps from 0x10 to 0x0C do not produce any changes in digital volume,
while each of the remaining 96 steps from 0x0C (+12 dB) to 0x00 (0 dB) causes a 0.125-dB reduction in digital volume. If
digital boost is enabled, the soft ramp does not step through the +12-dB settings.
4.5 Digital Microphone (DMIC) Interface
The digital mic interface can be used to collect pulse-E (PDM) audio data from the integrated ADCs of one or two digital
mics. The following sections describe how to use the interface.
f
c
1
2
 1 M   0.01 F  
------------------------------------------------------ 15.9 Hz = =
f
c
1
2
 50 k   0.1 F  
---------------------------------------------------- 31.83 Hz = =