Cirrus Logic CS53L30 - Manual (Page 24)

24 DS992F1
CS53L30
4.5 Digital Microphone (DMIC) Interface
4.5.1 DMIC Interface Description
The DMIC interface consists of a serial-data shift clock output (DMICx_SCLK) and a serial data input (DMICx_SD).
Fig. 2-2 shows how to connect two digital mics (“Left” and “Right”) to the CS53L30. The clock is fanned out to both digital
mics, and both digital mics’ data outputs share a single signal line to the CS53L30. To share a single line, the digital mics
tristate their output during one phase of the clock (high or low part of cycle, depending on how they are configured via their
L/R input). The CS53L30 defaults to mono digital mic input (left channel or rising edge of DMICx_SCLK data only). When
DMIC1_STEREO_ENB or DMIC2_STEREO_ENB (see p. 52 ) is cleared, then both edges of DMICx_SCLK are used to
capture stereo data; Alternating between one digital mic outputting a bit of data and then the other mic outputting a bit of
data, the digital mics time domain multiplex on the signal data line. Contention on the data line is avoided by entering the
high-impedance tristate faster than removing it.
The DMICx_SD signal can be held low through a weak pulldown (per Section 7.19 and Section 7.20 ) by its CS53L30 input.
When the DMIC interface is active, this pulling is not strong enough to affect the multiplexed data line significantly while it
is in tristate between data slots. While the interface is disabled and the data line is not driven, the weak pulling ensures
that the CS53L30 input avoids any power-consuming midrail voltage.
4.5.2 DMIC Interface Signaling
Fig. 4-8 shows the signaling on the DMIC interface. Notice how the left channel (A, or DATA1 channel) data from the “Left”
mic is sampled on the rising edge of the clock and the right channel (B, or DATA2 channel) data from the “Right” mic is
sampled on the falling edge.
Figure 4-8. Digital Mic Interface Signalling
4.5.3 DMIC Interface Clock Generation
Table 4-1 lists DMIC interface serial clock (DMICx_SCLK) nominal frequencies and their derivation from the internal
master clock.
Table 4-1. Digital Mic Interface Clock Generation
Post-MCLK_DIV MCLK Rate
(MHz)
MCLK_INT_
SCALE
ASP_RATE
(kHz) 1
Divide
Ratio
DMICx_SCLK Rate
(MHz)
DMICx_SCLK_DIV
Programming
5.6448 0 X 2 2.8224 0
4 1.4112 1
1 11.025 2 0.7056 0
4 0.3528 1
22.050 2 1.4112 0
4 0.7056 1
44.1 2 2.8224 0
4 1.4112 1
6.0000 0 X 2 3.0000 0
4 1.5000 1
1 8,11.025,12 2 0.7500 0
4 0.3750 1
16, 22.050,
24
2 1.5000 0
4 0.7500 1
32, 44.1, 48 2 3.0000 0
4 1.5000 1
DMIC_CLK
DMIC_SD
Left
(A, DATA1 )
Channel Data
Right
(B , DATA2)
Channel Data
Left
(A, DATA1)
Channel Data