Cirrus Logic CS4953xx - Manual (Page 84)

SDRAM/Flash Controller Interface
CS4953xx Hardware User’s Manual
DS732UM10 Copyright 2010 Cirrus Logic, Inc 8-6
DynamictREX
Configure the self refres exit time. Also known as Tsre
Bit 31:4 = 0 = Reserved
Bit 3:0 = Trex, where:
0x0 to 0xE = (n + 1) DSP clk cycles.
0xF = 16 DSP clk cycles.
Example:
Trex = 83 nS, HCLK = 120Mhz
Trex = 83 nS * 120 Mhz - 1 =10-1 = 0x9
0x81000064
0xHHHHHHHH
Default 0x00000009
DynamictAPR
Configure the last data out to active command time.
Bit 31:4 = 0 = Reserved
Bit 3:0 = Tapr, where:
0x0 to 0xE = (n + 1) DSP clk cycles.
0xF = 16 DSP clk cycles.
0x81000065
0xHHHHHHHH
Default 0x00000000
DynamictDAL
Configure the data-in to active command time.
Bit 31:4 = 0 = Reserved
Bit 3:0 = Tdal, where:
0x0 to 0xE = (n + 1) DSP clk cycles.
0xF = 16 DSP clk cycles.
Example:
Tdal = 6 CLKs, HCLK = 120Mhz
Tdal = 6-1 = 0x5
0x81000066
0xhHHHHHHH
Default 0x00000005
DynamictWR
Configure the write recovery time. Also known as Tdpl, Trwl
Bit 31:4 = 0 = Reserved
Bit 3:0 = Tdal, where:
0x0 to 0xE = (n + 1) DSP clk cycles.
0xF= 16 DSP clk cycles.
Example:
Twr = 2 CLKs, HCLK = 120Mhz
Twr = 2-1 = 0x1
0x81000067
0xHHHHHHHH
Default 0x00000001
DynamictRC
Configure the active to active command time.
Bit 31:5 = 0 = Reserved
Bit 4:0 = Trc, where:
0x0 to 0x1E = (n + 1) DSP clk cycles.
0x1F = 16 DSP clk cycles.
Example:
Trc = 65 nS, HCLK = 120Mhz
Trc = 65 nS * 120 Mhz -1 =7.8-1 = 0x7
0x81000068
0xHHHHHHHH
Default 0x00000007
Table 8-2. SDRAM/Flash Controller Parameters (Continued)
Mnemonic Hex Message