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Copyright 2010 Cirrus Logic, Inc.
DS732UM10
Figures
CS4953xx Hardware User’s Manual
Figure 3-8. I
2
C Write Flow Diagram ..............................................................................................................3-8
Figure 3-9. I
2
C Read Flow Diagram ............................................................................................................3-10
Figure 3-10. Sample Waveform for I
2
C Write Functional TIming ................................................................3-12
Figure 3-11. Sample Waveform for I
2
C Read Functional TIming ................................................................3-12
Figure 3-12. SPI Serial Control Port Internal Block Diagram ......................................................................3-13
Figure 3-13. Block Diagram of SPI System Bus..........................................................................................3-15
Figure 3-14. Address and Data Bytes .........................................................................................................3-16
Figure 3-15. SPI Write Flow Diagram..........................................................................................................3-17
Figure 3-16. SPI Read Flow Diagram .........................................................................................................3-18
Figure 3-17. Sample Waveform for SPI Write Functional Timing................................................................3-20
Figure 3-18. Sample Waveform for SPI Read Functional Timing ...............................................................3-20
Figure 5-1. DAI Port Block Diagram ..............................................................................................................5-3
Figure 5-2. I
2
S format (Rising Edge Valid SCLK)..........................................................................................5-4
Figure 5-3. Left-justified Format (Rising Edge Valid SCLK) ..........................................................................5-5
Figure 6-1. DSD Port Block Diagram ............................................................................................................6-2
Figure 7-1. DAO Block Diagram ....................................................................................................................7-2
Figure 7-2. I
2
S Compatible Serial Audio Formats (Rising Edge Valid) .........................................................7-3
Figure 7-3. Left-justified Digital Audio Formats (Rising Edge Valid DAO_SCLK) .........................................7-3
Figure 7-4. One-line Data Mode Digital Audio Formats ................................................................................7-4
Figure 8-1. SDRAM Interface Block Diagram................................................................................................8-1
Figure 9-1. LQFP-144, I
2
C Control, Serial FLASH, SDRAM, 7 DACs ..........................................................9-2
Figure 9-2. LQFP-144, SPI Control, Serial FLASH, SDRAM, 7 DACs ..........................................................9-3
Figure 9-3. LQFP-144, SPI Control, Serial FLASH, SDRAM, 8 DACs ..........................................................9-4
Figure 9-4. LQFP-144, I
2
C Control, Parallel Flash, SDRAM, 8 DACs ..........................................................9-5
Figure 9-5. LQFP-128, SPI Control, Parallel Flash, SDRAM, 8 DACs ..........................................................9-6
Figure 9-6. LQFP-128, I
2
C Control, Serial FLASH, DSD Audio Input, SDRAM, 7 DACs..............................9-7
Figure 9-7. LQFP-144, SPI Control, Serial FLASH, DSD Audio Input, SDRAM, 7 DACs .............................9-8
Figure 9-8. LQFP-144, SPI Control, Serial FLASH, DSD Audio Input, SDRAM, 7 DACs .............................9-9
Figure 9-9. PLL Filter Topology ...................................................................................................................9-12
Figure 9-10. Crystal Oscillator Circuit Diagram ...........................................................................................9-13
Figure 9-11. 144-Pin LQFP Pin Layout .......................................................................................................9-15
Figure 9-12. 128-Pin LQFP Pin Layout .......................................................................................................9-16
