Table 3-2. serial control port spi signals -14 – Cirrus Logic CS4953xx User Manual
Page 46
SPI Port
CS4953xx Hardware User’s Manual
DS732UM10
Copyright 2010 Cirrus Logic, Inc
3-14
shows the signal names, descriptions, and pin number of the signals associated with the SPI
Serial Control Port on the CS4953xx.
Table 3-2. Serial Control Port SPI Signals
Pin Name
Pin Description
LQFP-144
Pin #
LQFP-128
Pin #
Pin Type
SCP1_CS
SPI Chip Select, Active Low
In serial SPI slave mode, this pin is used as the active-low chip-
select input signal. In SPI serial master mode, if this pin is
driven low by another master device on the bus, it will cause a
mode fault to occur.
96
6
Input
SCP1_CLK
SPI Control Port Bit Clock
In master mode, this pin serves as the serial control clock
output. In serial slave mode, this pin serves as the serial control
clock input.
99
126
I/O
SCP1_MOSI
SPI Mode Master Data Output/Slave Data Input
SCP1_MOSI in SPI slave mode this pin serves an the data
input, in SPI master mode this pin serves as the data output.
95
3
I/O
SCP1_MISO
SPI Mode Master Data Input/Slave Data Output
In SPI slave mode this pin serves as the data input. In SPI
master mode this pin serves as the data output.
97
2
I/O
SCP1_IRQ
Serial Control Port Data Ready Interrupt Request Output, Active
Low
This pin is driven low when the DSP has a message for the host
to read. The pin will go high when the host has read the
message and the DSP has no further messages. This pin
reflects the state of the SCP1 port Transmit Buffer Empty Flag.
100
4
Open
Drain
SCP1_BSY
Serial Control Port 1 Input Busy, Output, Active Low
This pin is driven low when the control port’s receive buffer is
full. This pin reflects the state of the SCP1 or PCP Receive
Buffer Full Fag.
102
128
Open
Drain
SCP2_CS
SPI Chip Select, Active Low
In serial SPI slave mode, this pin is used as the active-low chip-
select input signal. In SPI serial master mode, if this pin is
driven low by another master device on the bus, it will cause a
mode fault to occur.
104
7
Input
SCP2_CLK
SPI Control Port Bit Clock
In master mode, this pin serves as the serial control clock
output. In serial slave mode, this pin serves as the serial control
clock input.
103
1
I/O
SCP2_MISO
SPI Mode Master Data Input/Slave Data Output
In SPI slave mode this pin serves as the data input. In SPI
master mode this pin serves as the data output.
105
2
I/O
SCP2_MOSI
SPI Mode Master Data Output/Slave Data Input
SCP2_MOSI in SPI slave mode this pin serves as the data
input, in SPI master mode this pin serves as the data output.
106
3
I/O
EE_CS
Master Mode Serial EPROM Chip Select, Active Low
6, 14, 25,
or 121
38, 46, or
14
Output