Cirrus Logic CS4953xx - Manual (Page 7)

DS732UM10 Copyright 2010 Cirrus Logic, Inc. vii
Tables
CS4953xx Hardware User’s Manual
Tables
Table 2-1. Operation Modes..........................................................................................................................2-3
Table 2-2. SLAVE_BOOT message for CS4953xx .....................................................................................2-10
Table 2-3. HCMB_PARALLEL Message for CS4953xx ..............................................................................2-10
Table 2-4. HCMB_I2C message for the CS4953xx.....................................................................................2-11
Table 2-5. HCMB_SPI message for CS4953xx ..........................................................................................2-11
Table 2-6. GPIO Pins Available as EE_CS in HCMB..................................................................................2-12
Table 2-7. SOFT_RESET message for CS4953xx .....................................................................................2-12
Table 2-8. Boot Read Messages from CS4953xx .......................................................................................2-12
Table 2-9. Boot Command Messages for CS4953xx ..................................................................................2-13
Table 2-10. SOFTBOOT Message..............................................................................................................2-14
Table 2-11. SOFTBOOT_ACK Message ....................................................................................................2-14
Table 3-1. Serial Control Port 1 I
2
C Signals..................................................................................................3-3
Table 3-2. Serial Control Port SPI Signals ..................................................................................................3-14
Table 5-1. Digital Audio Input Port ................................................................................................................5-1
Table 5-2. Bursty Data Input (BDI) Pins ........................................................................................................5-4
Table 5-3. Input Data Format Configuration (Input Parameter A) .................................................................5-6
Table 5-4. Input SCLK Polarity Configuration (Input Parameter B)...............................................................5-7
Table 5-5. Input LRCLK Polarity Configuration (Input Parameter C) ............................................................5-8
Table 5-6. Input DAI Mode Configuration (Input Parameter D) .....................................................................5-8
Table 6-1. DSDl Audio Input Port ..................................................................................................................6-1
Table 7-1. Digital Audio Output (DAO1 & DAO2) Pins..................................................................................7-1
Table 7-2. Output Clock Mode Configuration (Parameter A) ........................................................................7-5
Table 7-3. DAO1 & DAO2 Clocking Relationship Configuration (Parameter B)............................................7-5
Table 7-4. Output DAO_SCLK/LRCLK Configuration (Parameter C) ...........................................................7-6
Table 7-5. Output Data Format Configuration (Parameter D) .......................................................................7-9
Table 7-6. Output DAO_LRCLK Polarity Configuration (Parameter E) .......................................................7-10
Table 7-7. Output DAO_SCLK Polarity Configuration (Parameter F) .........................................................7-10
Table 7-8. Output Channel Configuration (Parameter G)............................................................................7-11
Table 7-9. S/PDIF Transmitter Pins ............................................................................................................7-11
Table 7-10. S/PDIF Transmitter Configuration ............................................................................................7-12
Table 7-11. DSP Bypass Configuration.......................................................................................................7-12
Table 8-1. SDRAM Interface Signals ............................................................................................................8-2
Table 8-2. SDRAM/Flash Controller Parameters ..........................................................................................8-5
Table 9-1. Core Supply Pins .......................................................................................................................9-10
Table 9-2. I/O Supply Pins ..........................................................................................................................9-10
Table 9-3. Core and I/O Ground Pins..........................................................................................................9-11