Cirrus Logic CS4953xx - Manual (Page 68)

Digital Audio Output Port Description
CS4953xx Hardware User’s Manual
DS732UM10 Copyright 2010 Cirrus Logic, Inc 7-2
DAO1_SCLK is the bit clock used to clock data out on DAO1_DATA[3:0].
DAO1_LRCLK is the data framing clock whose frequency is equal to the sampling frequency for the
DAO1 data outputs.
DAO1_DATA[3:0] are the data outputs and are typically configured for outputting two channels of I
2
S or
left-justified PCM data. DAO1_DATA0 may also be configured to provide output for four or six channels of
PCM data. The DAO1_DATA3 (XMTA) pin can alternatively serve as an S/PDIF transmitter output.
DAO2_SCLK is the bit clock used to clock data out on DAO2_DATA[3:0].
DAO2_LRCLK is the data framing clock which has a frequency equal to the sampling frequency for the
DAO2 data outputs.
DAO2_DATA[3:0] are the data outputs and are typically configured for outputting two channels of I
2
S or
left-justified PCM data. DAO2_DATA0 may also be configured to provide output for four or six channels of
PCM data. The DAO2_DATA3 (XMTB) pin can alternatively serve as an S/PDIF transmitter output..
Figure 7-1. DAO Block Diagram
DAO1_DATA0
P
er
iphe
ra
l B
u
s t
o
D
M
A
DAO1_DATA0
DAO1_DATA1
DAO1_DATA1
DAO1_DATA2
DAO1_DATA2
DAO1_DATA3
DAO1_DATA3, XMTA
DAO2_DATA0
DAO2_DATA0
DAO2_DATA1
DAO2_DATA1
DAO2_DATA2
DAO2_DATA2
DAO2_DATA3
Cl
o
ck
Ma
na
ge
r
DAO_MCLK
DAO1_SCLK_LRCLK
DAO2_SCLK_LRCLK
SPDIF ENCODER
DAO2_DATA3, XMTB
SPDIF ENCODER