Cirrus Logic CS4953xx - Manual (Page 26)

Slave Boot Procedures
CS4953xx Hardware User’s Manual
DS732UM10 Copyright 2010 Cirrus Logic, Inc 2-12
The SPI clock is derived from the internal core clock. This clock can be divided down with the “c” 12-bit
divider variable. The command byte (the first byte to the SPI ROM) can be defined by the “s” variable. The
CS4953xx control port used for the HCMB_SPI can be configured by the ‘p’ variable. Finally, the “S”
variable configures the chip select used, according to
Table 2-6 below.
2.3.3.5 Soft Reset
The SOFT_RESET message is the message sent to the CS4953xx after all of the overlays have been
successfully booted. The SOFT_RESET leaves execution of the bootloader and begins execution of the
loaded overlays. The overlays can be configured once the SOFT_RESET message has been sent.
2.3.3.6 Messages Read from CS4953xx
Table 2-8 defines the boot read messages, in mnemonic and actual hex value, used in CS4953xx boot
sequences.
Note: There is a unique {ID} for every .uld file.
Table 2-6. GPIO Pins Available as EE_CS in HCMB
‘S’ Value Pin Name
LQFP-144
Pin #
LQFP-128
Pin #
0 GPIO20 6 38
1 GPIO23 14 46
2 GPIO25 25 -
3 GPIO0
1
1.GPIO0 as EE_CS can be used to load only one
.uld in HCMB mode. If multiple .uld files are to be
loaded, do not use GPIO0 as EE_CS in HCMB
Mode..
121 -
Table 2-7. SOFT_RESET message for CS4953xx
MNEMONIC VALUE
SOFT_RESET 0x4000 0000
SOFT_RESET_DSP_A 0x5000 0000
Table 2-8. Boot Read Messages from CS4953xx
MNEMONIC VALUE
BOOT_START 0x0000 0001
BOOT_SUCCESS 0x0000 0002
APP_START 0x0000 0004
BOOT_ERROR_CHECKSUM 0x0000 00FF
INVALID_BOOT_TYPE 0x0000 00FE
BOOT_FAILURE 0x0000 00F8
APPLICATION_FAILURE 0xF0{ID} 0000