Rainbow Electronics DS1875 - Manual (Page 27)

DS1875
Stability and Compensation Component Selection
The components connected to the COMP pin (R COMP
and C COMP ) introduce a pole and zero that are neces-
sary for stable operation of the PWM controller
(Figure 12).
The dominant pole, POLE1, is formed by the output
impedance of the error amplifier (R
EA ) and C COMP . The
zero formed by the components on COMP, ZERO1, is
selected to cancel POLE2 formed by the output filter
cap C3 and output load R
LOAD
. The additional pole,
POLE3, formed by R1 and C3 should be at least a
decade past the crossover frequency to not affect sta-
bility. The following formulas can be used to calculate
the poles and zero for the application shown in
Figure 12.
POLE1 (dominant pole) = 1/(2
π × R
EA
× C
COMP )
ZERO1 (compensation zero) = 1/(2
π × R
COMP
× C
COMP )
POLE2 (output load pole) =
POLE3 (output filter pole) = 1/(2
π × R1 × C3)
The DC open-loop gain is given by:
Where:
R EA = 260M
Ω
G
M
= 425µS
R LOAD = Parallel combination of feedback network and
load resistance
V OUT = Output of DC-DC converter
V IN = DC-DC converter input voltage
V FB = Feedback voltage at the FB pin
T = Time period of switching frequency (seconds)
L = Inductor value (henries)
DAC1 Output
The DAC1 output has a full-scale 2.5V range with 8 bits
of resolution, and is programmed through the I
2 C inter-
face. The DAC1 setting is nonvolatile and password-2
(PW2) protected.
M4DAC Output
The M4DAC output has a full-scale 2.5V range with 8
bits of resolution, and is controlled by an LUT indexed
by the MON4 voltage. The M4DAC LUT (Table 06h) is
nonvolatile and PW2 protected. See the
Memory
Organization section for details. The recalled value is
either 16-bit or 32-bit depending on bits DBL_SB and
UP_LOWB in Table 02h, Register C7h.
Digital I/O Pins
Five digital I/O pins are provided for additional monitor-
ing and control. By default the LOSI pin is used to con-
vert a standard comparator output for loss of signal
(LOSI) to an open-collector output. This means the mux
shown on the block diagram by default selects the LOSI
pin as the source for the D0 output transistor. The level
of the D0 pin can be read in the STATUS byte (Lower
Memory, Register 6Eh) as the LOS STATUS bit. The
LOS STATUS bit reports back the logic level of the D0
pin, so an external pullup resistor must be provided for
this pin to output a high level. The LOSI signal can be
inverted before driving the open-drain output transistor
using the XOR gate provided. The MUX LOS allows the
D0 pin to be used identically to the D1, D2, and D3
pins. However, the mux setting (stored in the EEPROM)
does not take effect until V
CC > V POA , allowing the EEP-
ROM to recall. This requires the LOSI pin to be ground-
ed for D0 to act identical to the D1, D2, and D3 pins.
Digital pins D1, D2, and D3 can be used as inputs or
outputs. External pullup resistors must be provided to
realize high-logic levels. The DIN byte indicates the
logic levels of these input pins (Lower Memory, Register
79h), and the open-drain outputs can be controlled
using the DOUT byte (Lower Memory, Register 78h).
When V
CC < V POA , these outputs are high impedance.
Once V CC
≥ V
POA , the outputs go to the power-on
default state stored in the DPU byte (Table 02h, Register
C0h). The EEPROM-determined default state of the pin
can be modified with PW2 access. After the default
state has been recalled, the SRAM registers controlling
outputs can be modified without password access. This
allows the outputs to be used to control serial interfaces
without wearing out the default EEPROM setting.
D2 can be configured as the output of a quick-trip mon-
itor for MON3. The main application is to quickly shut
down the PWM converter and discharge the voltage
created by the converter. This is shown in the typical
application circuit.
AOL G R
V V
V V
V V
M EA
FB IN
OUT IN
OUT IN = Ч Ч Ч
Ч
Ч −
Ч
−
0 85
2
2 . V V
R T
L
OUT
LOAD Ч
Ч
Ч
⎛
⎝⎜ ⎞
⎠⎟
2
2 1
2 2 3
Ч −
−
Ч
Ч Ч +
( )
V V
V V R C C
OUT IN
OUT IN LOAD
π
PON Triplexer and SFP Controller
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