Rainbow Electronics DS2151Q - Manual (Page 9)

DS2151Q
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RSDW RCR2.5 RSYNC Double–Wide.
0=do not pulse double–wide in signaling frames
1=do pulse double–wide in signaling frames (note: this bit must be set to
zero when RCR2.4=1 or when RCR2.3=1)
RSM RCR2.4 RSYNC Mode Select.
0=frame mode (see the timing in Section 13)
1=multiframe mode (see the timing in Section 13)
RSIO RCR2.3 RSYNC I/O Select.
0=RSYNC is an output
1=RSYNC is an input (only valid if elastic store enabled) (note: this bit must
be set to zero when CCR1.2=0)
RD4YM RCR2.2 Receive Side D4 Yellow Alarm Select.
0=zeros in bit 2 of all channels
1=a one in the S–bit position of frame 12
FSBE RCR2.1 PCVCR Fs Bit Error Report Enable.
0=do not report bit errors in Fs bit position; only Ft bit position
1=report bit errors in Fs bit position as well as Ft bit position
MOSCRF RCR2.0 Multiframe Out of Sync Count Register Function Select.
0=count errors in the framing bit position
1=count the number of multiframes out of sync
TCR1: TRANSMIT CONTROL REGISTER 1 (Address=35 Hex)
(MSB) (LSB)
LOTCMC TFPT TCPT RBSE GB7S TLINK TBL TYEL
SYMBOL POSITION NAME AND DESCRIPTION
LOTCMC TCR1.7 Loss Of Transmit Clock Mux Control. Determines whether the transmit
side formatter should switch to the ever present RCLK if the TCLK input
should fail to transition (see Figure 1–1 for more details).
0=do not switch to RCLK if TCLK stops
1=switch to RCLK if TCLK stops
TFPT TCR1.6 Transmit Framing Pass Through. (see note below)
0=Ft or FPS bits sourced internally
1=Ft or FPS bits sampled at TSER during F–bit time
TCPT TCR1.5 Transmit CRC Pass Through. (see note below)
0=source CRC6 bits internally
1=CRC6 bits sampled at TSER during F–bit time
RBSE TCR1.4 Robbed–Bit Signaling Enable. (see note below)
0=no signaling is inserted in any channel
1=signaling is inserted in all channels (the TTR registers can be used to
block insertion on a channel by channel basis)
GB7S TCR1.3 Global Bit 7 Stuffing. (see note below)
0=allow the TTR registers to determine which channels containing all zeros
are to be Bit 7 stuffed
1=force Bit 7 stuffing in all zero byte channels regardless of how the TTR
registers are programmed