Rainbow Electronics DS2151Q - Manual (Page 19)

DS2151Q
022697 19/46
5.0 ERROR COUNT REGISTERS
There are a set of three counters in the DS2151Q that
record bipolar violations, excessive zeros, errors in the
CRC6 code words, framing bit errors, and number of
multiframes that the device is out of receive synchro-
nization. Each of these three counters are automatically
updated on one second boundaries as determined by
the one second timer in Status Register 2 (SR2.5).
Hence, these registers contain performance data from
the previous second. The user can use the interrupt
from the one second timer to determine when to read
these registers. The user has a full second to read the
counters before the data is lost. All three counters will
saturate at their respective maximum counts and they
will not rollover (note: only the Line Code Violation
Count Register has the potential to overflow).
5.1 Line Code Violation Count Register
(LCVCR)
Line Code Violation Count Register 1 (LCVCR1) is the
most significant word and LCVCR2 is the least signifi-
cant word of a 16–bit counter that records code viola-
tions (CVs). CVs are defined as Bipolar Violations
(BPVs) or excessive zeros. See Table 5–1 for details of
exactly what the LCVCRs count. If the B8ZS mode is
set for the receive side via CCR2.2, then B8ZS code
words are not counted. This counter is always enabled;
it is not disabled during receive loss of synchronization
(RLOS=1) conditions.
LCVCR1: LINE CODE VIOLATION COUNT REGISTER 1 (Address=23 Hex)
LCVCR2: LINE CODE VIOLATION COUNT REGISTER 2 (Address=24 Hex)
(MSB) (LSB)
LCV15 LCV14 LCV13 LCV12 LCV11 LCV10 LCV9 LCV8
LCV7 LCV6 LCV5 LCV4 LCV3 LCV2 LCV1 LCV0
SYMBOL POSITION NAME AND DESCRIPTION
LCV15 LCVCR1.7 MSB of the 16–Bit code violation count
LCV0 LCVCR2.0 LSB of the 16–Bit code violation count
LINE CODE VIOLATION COUNTING ARRANGEMENTS Table 5–1
COUNT EXCESSIVE
ZEROS?
(RCR1.7)
B8ZS ENABLED?
(CCR2.2) WHAT IS COUNTED IN THE LCVCRs
no no BPVs
yes no BPVs + 16 consecutive zeros
no yes BPVs (B8ZS code words not counted)
yes yes BPVs + 8 consecutive zeros
5.2 Path Code Violation Count Register
(PCVCR)
When the receive side of the DS2151Q is set to operate
in the ESF framing mode (CCR2.3=1), PCVCR will
automatically be set as a 12–bit counter that will record
errors in the CRC6 code words. When set to operate in
the D4 framing mode (CCR2.3=0), PCVCR will auto-
matically count errors in the Ft framing bit position. Via
the RCR2.1 bit, the DS2151Q can be programmed to
also report errors in the Fs framing bit position. The
PCVCR will be disabled during receive loss of synchro-
nization (RLOS=1) conditions. See Table 5–2 for a
detailed description of exactly what errors the PCVCR
counts.
LCVCR1
LCVCR2