Rainbow Electronics DS2151Q - Manual (Page 7)

DS2151Q
022697 7/46
63 R Receive Signaling Register 4. 73 R/W Transmit Signaling Register 4.
64 R Receive Signaling Register 5. 74 R/W Transmit Signaling Register 5.
65 R Receive Signaling Register 6. 75 R/W Transmit Signaling Register 6.
66 R Receive Signaling Register 7. 76 R/W Transmit Signaling Register 7.
67 R Receive Signaling Register 8. 77 R/W Transmit Signaling Register 8.
68 R Receive Signaling Register 9. 78 R/W Transmit Signaling Register 9.
69 R Receive Signaling Register 10. 79 R/W Transmit Signaling Register 10.
6A R Receive Signaling Register 11. 7A R/W Transmit Signaling Register 11.
6B R Receive Signaling Register 12. 7B R/W Transmit Signaling Register 12.
6C R/W Receive Channel Blocking Reg-
ister 1. 7C R/W Line Interface Control Register.
6D R/W Receive Channel Blocking Reg-
ister 2. 7D R/W Test Register. (2)
6E R/W Receive Channel Blocking Reg-
ister 3. 7E R/W Transmit FDL Register.
6F R/W Interrupt Mask Register 2. 7F R/W Interrupt Mask Register 1.
NOTES:
1. Address 25 also contains Multiframe Out of Sync Count Register 1.
2. The Test Register is used only by the factory; this register must be cleared (set to all zeros) on power–up initializa-
tion to insure proper operation.
2.0 PARALLEL PORT
The DS2151Q is controlled via a multiplexed bidirec-
tional address/data bus by an external microcontroller
or microprocessor. The DS2151Q can operate with
either Intel or Motorola bus timing configurations. If the
BTS pin is tied low, Intel timing will be selected; if tied
high, Motorola timing will be selected. All Motorola bus
signals are listed in parenthesis (). See the timing dia-
grams in the A.C. Electrical Characteristics for more
details. The multiplexed bus on the DS2151Q saves
pins because the address information and data informa-
tion share the same signal paths. The addresses are
presented to the pins in the first portion of the bus cycle
and data will be transferred on the pins during second
portion of the bus cycle. Addresses must be valid prior
to the falling edge of ALE(AS), at which time the
DS2151Q latches the address from the AD0 to AD7
pins. Valid write data must be present and held stable
during the later portion of the DS or WR pulses. In a read
cycle, the DS2151Q outputs a byte of data during the
latter portion of the DS or RD pulses. The read cycle is
terminated and the bus returns to a high impedance
state as RD transitions high in Intel timing or as DS tran-
sitions low in Motorola timing. The DS2151Q can also
be easily connected to non–multiplexed buses. Please
see the separate Application Note for a detailed discus-
sion of this topic.
3.0 CONTROL REGISTERS
The operation of the DS2151Q is configured via a set of
eight registers. Typically, the control registers are only
accessed when the system is first powered up. Once
the DS2151Q has been initialized, the control registers
will only need to be accessed when there is a change in
the system configuration. There are two Receive Con-
trol Registers (RCR1 and RCR2), two Transmit Control
Registers (TCR1 and TCR2), a Line Interface Control
Register (LICR), and three Common Control Registers
(CCR1, CCR2, and CCR3). Seven of the eight registers
are described below. The LICR is described in
Section 12.