Rainbow Electronics DS2151Q - Manual (Page 21)

DS2151Q
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NOTES:
1. The lower nibble of the counter at address 25 is used by the Path Code Violation Count Register.
2. MOSCR counts either errors in framing bit position (RCR2.0=0) or the number of multiframes out of sync
(RCR2.0=1).
MULTIFRAMES OUT OF SYNC COUNTING ARRANGEMENTS Table 5–3
FRAMING MODE
(CCR2.3)
COUNT MOS OR
F–BIT ERRORS?
(RCR2.0) WHAT IS COUNTED IN THE MOSCRs
D4 MOS number of multiframes out of sync
D4 F–Bit errors in the Ft pattern
ESF MOS number of multiframes out of sync
ESF F–Bit errors in the FPS pattern
6.0 FDL/FS EXTRACTION AND INSERTION
The DS2151Q has the ability to extract/insert data from/
into the Facility Data Link (FDL) in the ESF framing
mode and from/into Fs bit position in the D4 framing
mode. Since SLC–96 utilizes the Fs bit position, this
capability can also be used in SLC–96 applications.
The operation of the receive and transmit sections will
be discussed separately.
6.1 Receive Section
In the receive section, the recovered FDL bits or Fs bits
are shifted bit–by–bit into the Receive FDL register
(RFDL). Since the RFDL is 8 bits in length, it will fill up
every 2 ms (8 times 250 us). The DS2151Q will signal
an external microcontroller that the buffer has filled via
the SR2.4 bit. If enabled via IMR2.4, the INT2 pin will
toggle low indicating that the buffer has filled and needs
to be read. The user has 2 ms to read this data before it
is lost. If the byte in the RFDL matches either of the
bytes programmed into the RFDLM1 or RFDLM2 regis-
ters, then the SR2.2 bit will be set to a one and the INT2
pin will be toggled low if enabled via IMR2.2. This fea-
ture allows an external microcontroller to ignore the FDL
or Fs pattern until an important event occurs.
The DS2151Q also contains a zero destuffer which is
controlled via the CCR2.0 bit. In both ANSI T1.403 and
TR54016, communications on the FDL follows a subset
of a LAPD protocol. The LAPD protocol states that no
more than 5 ones should be transmitted in a row so that
the data does not resemble an opening or closing flag
(01111110) or an abort signal (11111111). If enabled via
CCR2.0, the DS2151Q will automatically look for 5 ones
in a row, followed by a zero. If it finds such a pattern, it
will automatically remove the zero. If the zero destuffer
sees six or more ones in a row followed by a zero, the
zero is not removed. The CCR2.0 bit should always be
set to a one when the DS2151Q is extracting the FDL.
More on how to use the DS2151Q in FDL and SLC–96
applications is covered in a separate Application Note.
Also, contact the factory for C code software that
implements both ANSI T1.403 and AT&T TR54016.
RFDL: RECEIVE FDL REGISTER (Address=28 Hex)
(MSB) (LSB)
RFDL7 RFDL6 RFDL5 RFDL4 RFDL3 RFDL2 RFDL1 RFDL0
SYMBOL POSITION NAME AND DESCRIPTION
RFDL7 RFDL.7 MSB of the Received FDL Code
RFDL0 RFDL.0 LSB of the Received FDL Code
The Receive FDL Register (RFDL) reports the incoming
Facility Data Link (FDL) or the incoming Fs bits. The
LSB is received first.