Rainbow Electronics DS2151Q - Manual (Page 27)

DS2151Q
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boundary, then RCR2.4 must be set to one. If the user
selects to apply a 2.048 MHz clock to the SYSCLK pin,
then the data output at RSER will be forced to all ones
every fourth channel and the F–bit will be deleted.
Hence channels 1, 5, 9, 13, 17, 21, 25, and 29 (timeslots
0, 4, 8, 12, 16, 20, 24, and 28) will be forced to a one.
Also, in 2.048 MHz applications, the RCHBLK output
will be forced high during the same channels as the
RSER pin. See Section 13 for more details. This is use-
ful in T1 to CEPT (E1) conversion applications. If the
386–bit elastic buffer either fills or empties, a controlled
slip will occur. If the buffer empties, then a full frame of
data (193 bits) will be repeated at RSER and the SR1.4
and RIR1.3 bits will be set to a one. If the buffer fills, then
a full frame of data will be deleted and the SR1.4 and
RIR1.4 bits will be set to a one.
10.2 Transmit Side
The transmit side elastic store can only be used if the
receive side elastic store is enabled. The operation of
the transmit elastic store is very similar to the receive
side; both have controlled slip operation and both can
operate with either a 1.544 MHz or a 2.048 MHz
SYSCLK. When the transmit elastic store is enabled,
both the SYSCLK and RSYNC signals are shared by
both the elastic stores. Hence, they will have the same
backplane PCM frame and data structure. Controlled
slips in the transmit elastic store are reported in the
RIR2.5 bit and the direction of the slip is reported in the
RIR2.3 and RIR2.4 bits.
10.3 Minimum Delay Synchronous SYSCLK
Mode
In applications where the DS2151Q is connected to
backplanes that are frequency locked to the recovered
T1 clock (i.e., the RCLK output), the full two frame depth
of the onboard elastic stores is really not needed. In
fact, in some delay sensitive applications, the normal
two frame depth may be excessive. If the CCR3.7 bit is
set to one, then the receive elastic store (and also the
transmit elastic store if it is enabled) will be forced to a
maximum depth of 32 bits instead of the normal 386 bits.
In this mode, the SYSCLK must be frequency locked to
RCLK and all of the slip contention logic in the DS2151Q
is disabled (since slips cannot occur). Also, since the
buffer depth is no longer two frames deep, the DS2151Q
must be set up to source either a frame or multiframe
pulse at the RSYNC pin. On power–up after the
SYSCLK has locked to the RCLK signal, the elastic
store reset bit (CCR3.6) should be toggled from a zero
to a one to insure proper operation.
11.0 RECEIVE MARK REGISTERS
The DS2151Q has the ability to replace the incoming
data, on a channel–by–channel basis with either an idle
code (7F Hex) or the digital milliwatt code which is an
eight byte repeating pattern that represents a 1 KHz
sine wave (1E/0B/0B/1E/9E/8B/8B/9E). The RCR2.7
bit will determine which code is used. Each bit in the
RMRs, represents a particular channel. If a bit is set to a
one, then the receive data in that channel will be
replaced with one of the two codes. If a bit is set to zero,
no replacement occurs.
RMR1/RMR2/RMR3: RECEIVE MARK REGISTERS (Address=2D to 2F Hex)
(MSB) (LSB)
CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17
SYMBOL POSITION NAME AND DESCRIPTION
CH24 RMR3.7 Receive Channel Blocking Registers.
0=do not affect the receive data associated with this channel
CH1 RMR1.0 1=replace the receive data associated with this channel with either the idle
code or the digital milliwatt code (depends on the RCR2.7 bit)
RMR1 (2D)
RMR2 (2E)
RMR3 (2F)