Rainbow Electronics DS2151Q - Manual (Page 37)

DS2151Q
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5. TLINK data (FDL bits) is sampled during the F-bit time of odd frame and inserted into the outgoing T1 stream if
enabled via TCR1.2.
6. ZBTSI mode is enabled (TCR2.5=1).
7. TLINK data (Z bits) is sampled during the F-bit time of frame 1, 5, 9, 13, 17, and 21 and inserted into the outgoing
stream if enabled via TCR1.2.
TRANSMIT SIDE BOUNDARY TIMING (WITH ELASTIC STORE(S) DISABLED) Figure 13–8
TCLK
TSER 1
TSYNC 1
TSYNC 2
TCHCLK
CHANNEL 2
LSB MSB LSB MSB F
CHANNEL 1
LSB MSB
TCHBLK 3
TLCLK
TLINK
Don’t Care
NOTES:
1. TSYNC is in the input mode (TCR2.2=0).
2. TSYNC is in the output mode (TCR2.2=1).
3. TCHBLK is programmed to block channel 1.
4. See Figures 13–4 and 13–5 for details on timing with the transmit side elastic store enabled.