Rainbow Electronics DS2151Q User Manual
Page 23
DS2151Q
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7.0 SIGNALING OPERATION
The Robbed–Bit signaling bits embedded in the T1
stream can be extracted from the receive stream and
inserted into the transmit stream by the DS2151Q.
There is a set of 12 registers for the receive side (RS1 to
RS12) and 12 registers on the transmit side (TS1 to
TS12). The signaling registers are detailed below. The
CCR1.5 bit is used to control the robbed signaling bits
as they appear at RSER. If CCR1.5 is set to zero, then
the robbed signaling bits will appear at RSER in their
proper position as they are received. If CCR1.5 is set to
a one, then the robbed signaling bit positions will be
forced to a one at RSER.
RS1 TO RS12: RECEIVE SIGNALING REGISTERS (Address=60 to 6B Hex)
(MSB)
(LSB)
A(8)
A(7)
A(6)
A(5)
A(4)
A(3)
A(2)
A(1)
A(16)
A(15)
A(14)
A(13)
A(12)
A(11)
A(10)
A(9)
A(24)
A(23)
A(22)
A(21)
A(20)
A(19)
A(18)
A(17)
B(8)
B(7)
B(6)
B(5)
B(4)
B(3)
B(2)
B(1)
B(16)
B(15)
B(14)
B(13)
B(12)
B(11)
B(10)
B(9)
B(24)
B(23)
B(22)
B(21)
B(20)
B(19)
B(18)
B(17)
A/C(8)
A/C(7)
A/C(6)
A/C(5)
A/C(4)
A/C(3)
A/C(2)
A/C(1)
A/C(16)
A/C(15)
A/C(14)
A/C(13)
A/C(12)
A/C(11)
A/C(10)
A/C(9)
A/C(24)
A/C(23)
A/C(22)
A/C(1)
A/C(20)
A/C(19)
A/C(18)
A/C(17)
B/D(8)
B/D(7)
B/D(6)
B/D(5)
B/D(4)
B/D(3)
B/D(2)
B/D(1)
B/D(16)
B/D(15)
B/D(14)
B/D(13)
B/D(12)
B/D(11)
B/D(10)
B/D(9)
B/D(24)
B/D(23)
B/D(22)
B/D(21)
B/D(20)
B/D(19)
B/D(18)
B/D(17)
SYMBOL
POSITION
NAME AND DESCRIPTION
D(24)
RS12.7
Signaling Bit D in Channel 24
A(1)
RS1.0
Signaling Bit A in Channel 1
Each Receive Signaling Register (RS1 to RS12) reports
the incoming Robbed–Bit signaling from eight DS0
channels. In the ESF framing mode, there can be up to
four signaling bits per channel (A, B, C, and D). In the D4
framing mode, there are only two framing bits per chan-
nel (A and B). In the D4 framing mode, the DS2151Q will
replace the C and D signaling bit positions with the A and
B signaling bits from the previous multiframe. Hence,
whether the DS2151Q is operated in either framing
mode, the user needs only to retrieve the signaling bits
every 3ms. The bits in the Receive Signaling Registers
are updated on multiframe boundaries so the user can
utilize the Receive Multiframe Interrupt in the Receive
Status Register 2 (SR2.7) to know when to retrieve the
signaling bits. The Receive Signaling Registers are fro-
zen and not updated during a loss of sync condition
(SR1.0=1). They will contain the most recent signaling
information before the “OOF” occurred.
RS1 (60)
RS2 (61)
RS3 (62)
RS4 (63)
RS5 (64)
RS6 (65)
RS7 (66)
RS8 (67)
RS9 (68)
RS10 (69)
RS11 (6A)
RS12 (6B)
RS1 (60)
RS2 (61)
RS3 (62)
RS4 (63)
RS5 (64)
RS6 (65)
RS7 (66)
RS8 (67)
RS9 (68)
RS10 (69)
RS11 (6A)
RS12 (6B)
RS1 (60)
RS2 (61)
RS3 (62)
RS4 (63)
RS5 (64)
RS6 (65)
RS7 (66)
RS8 (67)
RS9 (68)
RS10 (69)
RS11 (6A)
RS12 (6B)
RS1 (60)
RS2 (61)
RS3 (62)
RS4 (63)
RS5 (64)
RS6 (65)
RS7 (66)
RS8 (67)
RS9 (68)
RS10 (69)
RS11 (6A)
RS12 (6B)
RS1 (60)
RS2 (61)
RS3 (62)
RS4 (63)
RS5 (64)
RS6 (65)
RS7 (66)
RS8 (67)
RS9 (68)
RS10 (69)
RS11 (6A)
RS12 (6B)
RS1 (60)
RS2 (61)
RS3 (62)
RS4 (63)
RS5 (64)
RS6 (65)
RS7 (66)
RS8 (67)
RS9 (68)
RS10 (69)
RS11 (6A)
RS12 (6B)
RS1 (60)
RS2 (61)
RS3 (62)
RS4 (63)
RS5 (64)
RS6 (65)
RS7 (66)
RS8 (67)
RS9 (68)
RS10 (69)
RS11 (6A)
RS12 (6B)
RS1 (60)
RS2 (61)
RS3 (62)
RS4 (63)
RS5 (64)
RS6 (65)
RS7 (66)
RS8 (67)
RS9 (68)
RS10 (69)
RS11 (6A)
RS12 (6B)