Motorola CPCI-6115 - Manual (Page 130)

CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D)
Memory Maps Suggested PCI Memory Map
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1. This may be Flash Bank A or B depending on Flash Boot Bank Select jumper.
8.2.4 Suggested PCI Memory Map
The following table is the suggested PCI memory map for each PCI bus. This table reflects the
address map followed by the board level firmware at release time.
1E00 0000 1FFF FFFF 32 MB Unassigned
2000 0000 21FF FFFF 32 MB PCI Bus 0 P2P I/O Space
2200 0000 23FF FFFF 32 MB PCI Bus 0 P2P Memory Space 0
2400 0000 25FF FFFF 32 MB PCI Bus 0 P2P Memory Space 1
2600 0000 41FF FFFF 448 MB Unassigned
4200 0000 4303 FFFF 256 KB MV64360 Integrated SRAM
4304 0000 F1FF FFFF 2800 MB Unassigned
F200 0000 F3FF FFFF 32 MB PCI Bus 1 P2P Memory Space 1
F400 0000 FEFF FFFF 176 MB Unassigned
FF00 0000 FF7F FFFF 8 MB Device CS3*
FF80 0000 FFFF FFFF 8 MB Boot Flash 1
Table 8-3 Default PCI Address Map (continued)
PCI Address
Size Definition No
tes
Start End
Table 8-4 Suggested PCI Memory Map
PCI Address
Size Definition Start End
0000 0000 top_dram dram_size System Memory (onboard DRAM)
8000 0000 9FFF FFFF 512 MB PCI Bus 0 Memory Space
B000 0000 CFFF FFFF 512 MB PCI Bus 1 Memory Space
P2P Memory Space
F000 0000 F07F FFFF 8 MB PCI Bus 0 I/O Space
F080 0000 F0FF FFFF 8 MB PCI Bus 1 I/O Space
F100 0000 F10F FFFF 1 MB MV64360 Internal Registers
F110 0000 F11F FFFF 1 MB Device CS1* based I/O System
Regs/NVRAM/RTC/UART
F200 0000 F5FF FFFF 64 MB Flash Bank A
FF800 0000 FFFF FFFF 8 MB Flash Bank B