Freescale Semiconductor MC68HC08KH12 - Manual (Page 94)

Advance Information MC68HC(7)08KH12 — Rev. 1.1
94 Freescale Semiconductor
noise hit and the software must take appropriate action, depending on
the application. (See
8.7 Interrupts for information and precautions on
using interrupts.) The following conditions apply when the PLL is in
automatic bandwidth control mode:
• The ACQ bit (See 8.6.2 PLL Bandwidth Control Register
(PBWC) .) is a read-only indicator of the mode of the filter. (See
8.4.4 Acquisition and Tracking Modes .)
• The ACQ bit is set when the VCO frequency is within a certain
tolerance,
∆
TRK
, and is cleared when the VCO frequency is out of
a certain tolerance,
∆
UNT
. (See 8.9 Acquisition/Lock Time
Specifications for more information.)
• The LOCK bit is a read-only indicator of the locked state of the
PLL.
• The LOCK bit is set when the VCO frequency is within a certain
tolerance,
∆
LOCK
, and is cleared when the VCO frequency is out of
a certain tolerance
∆
UNL
. (See 8.9 Acquisition/Lock Time
Specifications for more information.)
• CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s
lock condition changes, toggling the LOCK bit. (See
8.6.1 PLL
Control Register (PCTL) .)
8.4.6 Programming the PLL
The following procedure shows how to program the PLL.
1. Choose the desired bus frequency, f
BUS
.
The relationship between the VCO frequency f
VCLK
and the bus
frequency f
BUS
is
The VCO frequency need to be at 48MHz for the USB module
reference clock.
Choose P = 0, 1, 2, or 3 for a bus frequency of 12MHz, 6MHz,
3MHz, or 1.5MHz respectively.
f
VCLK
2
P
------------- 4 f
BUS
× =
48MHz
2
P
-------------------- 4 f
BUS
Ч =