Freescale Semiconductor MC68HC08KH12 - Manual (Page 63)

MC68HC(7)08KH12 — Rev. 1.1 Advance Information
Freescale Semiconductor 63
Figure 7-1. SIM Block Diagram
STOP/WAIT
CLOCK
CONTROL
CLOCK GENERATORS
POR CONTROL
RESET PIN CONTROL
SIM RESET STATUS REGISTER
INTERRUPT CONTROL
AND PRIORITY DECODE
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
SIMOSCEN (TO CGM)
CGMOUT (FROM CGM)
INTERNAL CLOCKS
MASTER
RESET
CONTROL
RESET
PIN LOGIC
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP TIMEOUT (FROM COP MODULE)
INTERRUPT SOURCES
CPU INTERFACE
RESET
CONTROL
SIM
COUNTER
COP CLOCK
CGMXCLK (FROM CGM)
÷2
USB RESET (FROM USB MODULE)