Freescale Semiconductor MC68HC08KH12 - Manual (Page 129)

MC68HC(7)08KH12 — Rev. 1.1 Advance Information
Freescale Semiconductor 129
TXDIE — HUB Endpoint 0 Transmit Interrupt Enable
This read/write bit enables the Transmit HUB Endpoint 0 to generate
CPU interrupt requests when the TXDF bit becomes set. Reset clears
the TXDIE bit.
1 = USB interrupt enabled for Transmit HUB Endpoint 0
0 = USB interrupt disabled for Transmit HUB Endpoint 0
RXDIE — HUB Endpoint 0 Receive Interrupt Enable
This read/write bit enables the Receive HUB Endpoint 0 to generate
CPU interrupt requests when the RXDF bit becomes set. Reset clears
the RXDIE bit.
1 = USB interrupt enabled for Receive HUB Endpoint 0
0 = USB interrupt disabled for Receive HUB Endpoint 0
TXDFR — HUB Endpoint 0 Transmit Flag Reset
Writing a logic 1 to this write only bit will clear the TXDF bit if it is set.
Writing a logic 0 to TXDFR has no effect. Reset clears this bit.
RXDFR — HUB Endpoint 0 Receive Flag Reset
Writing a logic 1 to this write only bit will clear the RXDF bit if it is set.
Writing a logic 0 to RXDFR has no effect. Reset clears this bit.
9.4.7 USB HUB Control Register 0 (HCR0)
Address: $005B
Bit 7 6 5 4 3 2 1 Bit 0
Read:
TSEQ STALL0 TXE RXE TPSIZ3 TPSIZ2 TPSIZ1 TPSIZ0
Write:
Reset: 0 0 0 0 0 0 0 0
Figure 9-8. USB HUB Control Register 0 (HCR0)