4 usb sie timing status register (sietsr), Usb sie timing status register (sietsr) – Freescale Semiconductor MC68HC08KH12 User Manual
Page 125
MC68HC(7)08KH12
—
Rev. 1.1
Advance Information
Freescale Semiconductor
125
SOFIE — Start Of Frame Interrupt Enable
This read/write bit enables the Start Of Frame to generate a USB
interrupt when the SOFF bit becomes set. Reset clears this bit.
1 = USB interrupt enabled for Start Of Frame
0 = USB interrupt disabled for Start Of Frame
EOF2IE — The Second End of Frame Point Interrupt Enable
This read/write bit enables the Second End Of Frame to generate a
USB interrupt when the EOF2F bit becomes set. Reset clears this bit.
1 = USB interrupt enabled for the Second End Of Frame Point
0 = USB interrupt disabled for the Second End Of Frame Point
EOPIE — End of Packet Detect Interrupt Enable
This read/write bit enables the USB to generate a interrupt request
when the EOPF bit becomes set. Reset clears the bit.
1 = USB interrupt enabled for End-of-Packet sequence detection
0 = USB interrupt disabled for End-of-Packet sequence detection
TRANIE — Bus Signal Transition Detect Interrupt Enable
This read/write bit enables the Signal Transition to generate a USB
interrupt when the TRANF bit becomes set. Reset clears this bit.
1 = USB interrupt enabled for Bus Signal Transition
0 = USB interrupt disabled for Bus Signal Transition
9.4.4 USB SIE Timing Status Register (SIETSR)
Address:
$0057
Bit 7
6
5
4
3
2
1
Bit 0
Read:
RSTF
0
LOCKF
0
0
0
0
0
Write:
RSTFR
LOCKFR
SOFFR
EOF2FR
EOPFR
TRANFR
Reset:
0**
0
0
0
0
0
0
0
= Unimplemented
0** = Reset by POR only
Figure 9-5. USB SIE Timing Status Register (SIETSR)