Freescale Semiconductor MC68HC08KH12 - Manual (Page 203)

MC68HC(7)08KH12 — Rev. 1.1 Advance Information
Freescale Semiconductor 203
12.8.2 Data Direction Register F (DDRF)
Data direction register F determines whether each port F pin is an input
or an output. Writing a logic one to a DDRF bit enables the output buffer
for the corresponding port F pin; a logic zero disables the output buffer.
DDRF[7:0] — Data Direction Register F Bits
These read/write bits control port F data direction. Reset clears
DDRF[7:0], configuring all port F pins as inputs.
1 = Corresponding port F pin configured as output
0 = Corresponding port F pin configured as input
NOTE: Avoid glitches on port F pins by writing to the port F data register before
changing data direction register F bits from 0 to 1.
Figure 12-3 shows the port F I/O logic.
Figure 12-21. Port F I/O Circuit
Address: $000B
Bit 7 6 5 4 3 2 1 Bit 0
Read:
DDRF7 DDRF6 DDRF5 DDRF4 DDRF3 DDRF2 DDRF1 DDRF0
Write:
Reset: 0 0 0 0 0 0 0 0
Figure 12-20. Data Direction Register F (DDRF)
READ DDRF ($000B)
WRITE DDRF ($000B)
RESET
WRITE PTF ($0009)
READ PTF ($0009)
PTFx
DDRFx
PTFx
INTERNAL
DAT
A B
U
S