FUJITSU MB86617A - Manual (Page 5)

LSI Specification MB86617A
Rev.1.0 Fujitsu VLSI
v
9.2. D ESCRIPTION OF E ACH I NSTRUCTION
............................................................................................................................................... 103
CHAPTER 10 INTERRUPT
..................................................................................................................................................................... 106
10.1. I NTERRUPT - FACTOR I NDICATOR R EGISTER & INTERRUPT - MASK S ETTING R EGISTER
.............................................................107
10.2. I NTERRUPT
.......................................................................................................................................................................................... 108
10.3. D ESCRIPTION OF I NTERRUPT
............................................................................................................................................................ 109
CHAPTER 11 OPERATION ...................................................................................................................................................................112
11.1. I NITIALIZATION ................................................................................................................................................................................ 113
11.2. S ELF -ID P ACKET R ECEIVING .........................................................................................................................................................114
11.2.1 Self-ID Packet Receive at Bus Reset Process .............................................................................................................115
11.2.2 Self-ID Packet Receive after Transmitting Ping Packet Ping................................................................................ 118
11.3. A SYNCHRONOUS P ACKET T RANSMITTING ................................................................................................................................. 120
11.4. A SYNCHRONOUS P ACKET R ECEIVING .........................................................................................................................................122
11.5. I SOCHRONOUS P ACKET T RANSMITTING ..................................................................................................................................... 125
11.6. I SOCHRONOUS P ACKET R ECEIVING .............................................................................................................................................128
CHAPTER 12 SYSTEM CONFIGURATION...................................................................................................................................130
12.1. R ECOMMENDED C ONNECTION FOR 1934 P ORT ( FOR ONE PORT ) .......................................................................................... 131
12.2. R ECOMMENDED C ONNECTION FOR C ABLE P OWER S UPPLY ..................................................................................................132
12.3. R ECOMMENDED C ONNECTION FOR B UILD - IN PLL L OOP F ILTER .........................................................................................133
12.4. C ONFIGURATION OF F EEDBACK C IRCUIT AT C RYSTAL O SCILLATOR ...................................................................................134