FUJITSU MB86617A - Manual (Page 112)

LSI S pecification MB86617A
Rev.1.0 Fujitsu VLSI
107
10.1. Interrupt-factor Indicator Register & interrupt-mask Setting Register
AD R/
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
R
INT
1
INT
2
INT
3
INT
4
INT
5
INT
6
INT
7
INT
8
INT
9
INT
10
INT
11
INT
12
INT
13
INT
14
INT
15
INT
16
06h
W interrupt-mask
R
INT
17
INT
18
INT
19
INT
20
INT
21
INT
22
INT
23
INT
24
INT
25
INT
26
INT
27
INT
28
INT
29
INT
30
INT
31
INT
32
08h
W Interrupt-mask
Intial Value ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
> interrupt-factor Indicate Register
This register indicate the interrupt content reported by this device. Do not indicate the interrupt code specified MASK. Do not reflect
its code to XINT terminal either.
> interrupt-mask setting register
This register masks the interrupt reported by this device. Do not report the interrupt if ‘1’ is set for Bit corresponding to interrupt factor.