FUJITSU MB86617A - Manual (Page 20)

LSI S pecification MB86617A
Rev.1.0 Fujitsu VLSI
15
IERRA O
Output pin for noticing error of receive data (on port A)
‘H’ active signal
IERRB O
Output pin for noticing error of receive data (on port B)
‘H’ active signal
DSSCLKA I Clock input pin for DSS data (27MHz)
DSSCLKB I Clock input pin for DSS data (27MHz)