Altera Stratix V Avalon-ST - Manual (Page 92)

Signal Direction Description
app_msi_num[4:0] Input MSI number of the Application Layer. This signal provides the
low order message data bits to be sent in the message data field of
MSI messages requested by
app_msi_req
. Only bits that are
enabled by the MSI Message Control register apply.
app_int_sts Input Controls legacy interrupts. Assertion of
app_int_sts
causes an
Assert_INTA message TLP to be generated and sent upstream.
Deassertion of
app_int_sts
causes a Deassert_INTA message
TLP to be generated and sent upstream.
app_int_ack Output This signal is the acknowledge for
app_int_sts
. It is asserted for
at least one cycle either when either of the following events occur:
• The
Assert_INTA
message TLP has been transmitted in
response to the assertion of the
app_int_sts
.
• The
Deassert_INTA
message TLP has been transmitted in
response to the deassertion of the
app_int_sts
signal.
Interrupts for Root Ports
Table 5-10: Interrupt Signals for Root Ports
Signal Direction Description
int_status[3:0] Output These signals drive legacy interrupts to the Application Layer as
follows:
• int_status[0]: interrupt signal A
• int_status[1]: interrupt signal B
• int_status[2]: interrupt signal C
• int_status[3]: interrupt signal D
serr_out Output System Error: This signal only applies to Root Port designs that
report each system error detected, assuming the proper enabling
bits are asserted in the
Root Control
and
Device Control
registers. If enabled,
serr_out
is asserted for a single clock cycle
when a system error occurs. System errors are described in the
PCI Express Base Specification 2.1 or 3.0 in the
Root Control
register.
Related Information
PCI Express Base Specification 2.1 or 3.0
5-40 Interrupts for Root Ports
UG-01097_avst
2014.12.15
Altera Corporation Interfaces and Signal Descriptions
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