Altera Stratix V Avalon-ST - Manual (Page 159)

Figure 8-9: Legacy Interrupt Deassertion
clk
app_int_sts
app_int_ack
Related Information
Correspondence between Configuration Space Registers and the PCIe Specification on page 6-1
Interrupts for Root Ports
In Root Port mode, the Stratix V Hard IP for PCI Express receives interrupts through two different
mechanisms:
• MSI—Root Ports receive MSI interrupts through the Avalon-ST RX TLP of type
MWr
. This is a memory
mapped mechanism.
• Legacy—Legacy interrupts are translated into TLPs of type
Message Interrupt
which is sent to the
Application Layer using the
int_status[3:0]
pins.
Normally, the Root Port services rather than sends interrupts; however, in two circumstances the Root
Port can send an interrupt to itself to record error conditions:
• When the AER option is enabled, the
aer_msi_num[4:0]
signal indicates which MSI is being sent to
the root complex when an error is logged in the AER Capability structure. This mechanism is an
alternative to using the
serr_out
signal. The
aer_msi_n um[4:0]
is only used for Root Ports and you
must set it to a constant value. It cannot toggle during operation.
• If the Root Port detects a Power Management Event, the
pex_msi_num[4:0]
signal is used by Power
Management or Hot Plug to determine the offset between the base message interrupt number and the
message interrupt number to send through MSI. The user must set
pex_msi_num[4:0]
to a fixed value.
The
Root Error Status
register reports the status of error messages. The
Root Error Status
register is
part of the PCI Express AER Extended Capability structure. It is located at offset 0x830 of the Configura‐
tion Space registers.
UG-01097_avst
2014.08.18
Interrupts for Root Ports 8-7
Interrupts Altera Corporation
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