Altera Stratix V Avalon-ST - Manual (Page 34)

Figure 3-6: Timing for Memory Write and Read of Function 1
RxStMask_o
RxStSop_i
RxStEop_i
RxStValid_i
RxStReady_o
TxStReady_i
TxStSop_o
TxStEop_o
TxStValid_ o
rx_state[10:0]
rxavl_state[3:0]
rxcfg_state[4:0]
tx_state[1:0]
RxmAddress_0_o[19:0]
RxmFunc1Sel _o
RxmWrite_0_o
RxmWriteData_0_o[31:0]
RxmWaitRequest_0
RxmRead_0_ o
RxmReadDataValid_0 _
RxmReadData_0_i[31:0]
000 003
90030 00000
005 021 041 000 003 005 021 041 00
3 9 0 5
3
BABEFACE
BABEFACE
1 3
4
5 6
2
3-10 Timing for Memory Write and Read of Function 1 256-Bit Avalon-ST Interface
UG-01097_avst
2014.08.18
Altera Corporation Getting Started with the Configuration Space Bypass Mode Qsys Example Design
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