Altera Stratix V Avalon-ST - Manual (Page 10)

Figure 1-4: Example Design Preset Parameters
In this example design, the following parameters must be set to match the values set in the DUT:
• Targeted Device Family
• Lanes
• Lane Rate
• Application Clock Rate
• Port type
• Application Interface
• Tags supported
• Maximum payload size
The following Qsys example designs are available for the Stratix V Hard IP for PCI Express. You can
download them from the
/ ip/altera/altera_pcie/altera_pcie_hip_ast_ed/example_design/
directory:
• pcie_de_gen1_x4_ast64.qsys
• pcie_de_gen1_x8_ast128.qsys
• pcie_de_gen2_x8_ast256.qsys
• pcie_de_gen3_x1_ast64.qsys
• pcie_de_gen3_x4_ast128.qsys
• pcie_de_gen3_x8_ast256.qsys
• pcie_de_rp_gen1_x4_ast64.qsys
• pcie_de_rp_gen1_x8_ast128.qsys
UG-01097_avst
2014.12.15
Avalon-ST Example Designs 1-9
Datasheet Altera Corporation
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