Altera Stratix V Avalon-ST - Manual (Page 269)

Related Information
BFM Log and Message Procedures on page 17-43
Debugging Simulations
You can modify the following default testbench parameter settings to facilitate debugging.
• For Gen1 and Gen2 variants, you can disable 8B/10B encoding and decoding by setting
test_in[2] =
1
in altpcietb_bfm_top_rp.v.
• You can view the most important PIPE interface signals,
txdata
,
txdatak
,
rxdata
, and
txdatak
at the
following level of the design hierarchy:
altpcie__hip_pipen1b|
twentynm_hssi___pcie_hip_rbc
.
17-58 Debugging Simulations
UG-01097_avst
2014.12.15
Altera Corporation Testbench and Design Example
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