Altera Stratix V Avalon-ST - Manual (Page 85)

Related Information
Tradeoffs to Consider when Enabling Multiple Packets per Cycle on page 5-17
Root Port Mode Configuration Requests
If your Application Layer implements ECRC forwarding, it should not apply ECRC forwarding to
Configuration Type 0 packets that it issues on the Avalon-ST interface. There should be no ECRC
appended to the TLP, and the
TD
bit in the TLP header should be set to 0. These packets are processed
internally by the Hard IP block and are not transmitted on the PCI Express link.
To ensure proper operation when sending Configuration Type 0 transactions in Root Port mode, the
application should wait for the Configuration Type 0 transaction to be transferred to the Hard IP for PCI
Express Configuration Space before issuing another packet on the Avalon-ST TX port. You can do this by
waiting for the core to respond with a completion on the Avalon-ST RX port before issuing the next
Configuration Type 0 transaction.
Clock Signals
Table 5-5: Clock Signals
Signal Direction Description
refclk Input Reference clock for the IP core. It must have the frequency
specified under the System Settings heading in the parameter
editor. This is a dedicated free running input clock to the
dedicated
REFCLK
pin.
If your design meets the following criteria:
• Enables CvP
• Includes an additional transceiver PHY connected to the same
Transceiver Reconfiguration Controller
then you must connect
refclk
to the
mgmt_clk_clk
signal of the
Transceiver Reconfiguration Controller and the additional
transceiver PHY. In addition, if your design includes more than
one Transceiver Reconfiguration Controller on the same side of
the FPGA, they all must share the
mgmt_clk_clk
signal.
pld_clk Input Clocks the Application Layer. You can drive this clock with
coreclkout_hip
. If you drive
pld_clk
with another clock
source, it must be equal to or faster than
coreclkout_hip
.
coreclkout Output This is a fixed frequency clock used by the Data Link and
Transaction Layers. To meet PCI Express link bandwidth
constraints, this clock has minimum frequency requirements as
listed in Application Layer Clock Frequency for All Combination
of Link Width, Data Rate and Application Layer Interface Width
in the Reset and Clocks chapter .
UG-01097_avst
2014.12.15
Root Port Mode Configuration Requests 5-33
Interfaces and Signal Descriptions Altera Corporation
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